Procedural vs Continuous Assignments in Verilog

🔁 Procedural vs Continuous Assignments in Verilog

#

Verilog supports two main types of assignments, each used in different contexts for modeling hardware accurately.

⚙️ Continuous Assignment

#

• Uses the assign keyword
• Automatically updates the output whenever any input changes
• Describes combinational logic
• Signal must be a wire type

✅ Example:

#

assign y = a & b;

Key Points:

• Declared outside any always or initial block
• Suitable for simple logic and dataflow connections
• Behaves like a real physical wire

🔁 Procedural Assignment

#

• Defined inside initial or always blocks
• Describes sequential or controlled logic
• Signal must be a reg, integer, or real

✅ Example:

#

always @(posedge clk) begin
  count <= count + 1;
end

Key Points:

• Supports conditional logic (if, case, for)
• Must use = (blocking) or <= (non-blocking)
• Used for FSMs, registers, clocked logic

🧠 Summary Table

#

🔍 Tip: Common Error

#

reg y;
assign y = a & b;  // ❌ Error! Cannot drive reg from assign

➡️ Use wire with assign, or move logic into an always block.

💡 Understanding these two assignment types is essential for writing valid, synthesizable Verilog code.