Control Flow

🔄 Control Flow Statements in Verilog

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Control flow statements are used inside always or initial blocks to create conditional and sequential behavior.

✅ Common Constructs:

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🧰 The case Statement

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case provides a clean way to choose between multiple values.

✅ Basic Syntax:

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case (sel)
  2'b00: y = a;
  2'b01: y = b;
  2'b10: y = c;
  default: y = 1'b0;
endcase

🔹 casex and casez

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• casex: treats x and z in the case expression as wildcards
• casez: only treats z as wildcard, not x

🔁 Loops in Verilog

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Loops are typically used in testbenches, generate blocks, or initialization routines.

✅ Example – for loop:

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integer i;
initial begin
  for (i = 0; i < 8; i = i + 1)
    mem[i] = 0;
end

⚠️ Loops must converge during synthesis — avoid infinite or variable-length loops in RTL.