Module Definition, Usage, and Constructs

🧩 What is a Module in Verilog?

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A module is the fundamental building block in Verilog. It represents a self-contained hardware block — such as a gate, a flip-flop, a counter, or even an entire processor.

📦 Module Structure

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Modules promote hierarchical design, reuse, and testability.

🧱 Example Module

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module and_gate (
  input  wire a,
  input  wire b,
  output wire y
);
assign y = a & b;
endmodule

🔌 Module Port Types

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Ports define how a module communicates with the outside world.

🧱 Module Instantiation Styles

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🔹 Positional Mapping

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and_gate u1 (a, b, y);

⚠️ Port order must match definition exactly.

🔹 Named Mapping ✅ (Recommended)

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and_gate u1 (
  .a(in1),
  .b(in2),
  .y(out)
);

🔁 Multiple Instances

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and_gate u1 (.a(a1), .b(b1), .y(y1));
and_gate u2 (.a(a2), .b(b2), .y(y2));

🧪 Continuous Assignment: assign

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The assign keyword is used for combinational logic on wire-type signals.

assign y = a & b;

• Continuous: updates automatically when inputs change
• Can only be used with wire

🔁 Procedural Logic: always Block

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Used for logic that reacts to events (like clocks or conditions).

✅ Syntax

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always @(sensitivity_list) begin
  // statements
end

⚙️ always @(*) → Combinational Logic

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always @(*) begin
  case (sel)
    2'b00: y = a;
    2'b01: y = b;
    default: y = 0;
  endcase
end

• Use blocking assignment (=)

⏱️ always @(posedge clk) → Sequential Logic

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always @(posedge clk or posedge rst) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

• Use non-blocking assignment (<=)
• Models flip-flops and registers

🧬 Bitwise Operators

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Operate on each bit individually:

Don’t confuse with logical operators (&&, ||) which are single-bit.

🔗 Concatenation & Replication

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🔹 Concatenation

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assign bus = {addr, data};  // Combines two 8-bit signals into one 16-bit bus

🔹 Replication

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assign all_ones = {8{1'b1}};  // 8-bit vector of all 1s

📊 Summary Table

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🧠 Best Practices

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• ✅ Always use named port mapping
• 🧾 Use meaningful instance names: AND1, stage0, etc.
• 🎯 Follow consistent port direction and grouping
• ⚠️ Avoid mixing = and <= inside the same always block