Command-Line Input

📥 Command-Line Input in Verilog

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In Verilog testbenches, accepting command-line arguments makes your simulations parameterizable and reusable. This is especially useful for passing different seed, mode, or testcase values without modifying the testbench code.

🔹 $value$plusargs

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Used to capture arguments with values, passed in the form +ARG=VALUE.

$value$plusargs("SEED=%d", seed);

This call returns 1 and assigns the value to seed if +SEED=123 is passed at runtime. Otherwise, it returns 0.

✅ Example:

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integer seed;
initial begin
  if (!$value$plusargs("SEED=%d", seed)) begin
    seed = 42;  // Default fallback
  end
  $display("Using seed: %0d", seed);
end

🔹 $test$plusargs

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Checks for the presence of a flag (boolean-style argument) without an associated value.

if ($test$plusargs("VERBOSE")) begin
  $display("Verbose mode is ON.");
end

Returns 1 if +VERBOSE was passed, otherwise 0.

🖥️ Simulation Command

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vvp a.out +SEED=123 +VERBOSE

🧠 Summary Table

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