Compiler Directives & Macros

🧭 Verilog Compiler Directives & Macros

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Compiler directives in Verilog start with a backtick ` and instruct the compiler/simulator, not the synthesized hardware. They’re essential for conditional compilation, macro definitions, file inclusion, and simulation control.

📌 Common Compiler Directives

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🧠 Macro Example

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You can define constants or reusable code snippets with `define:

`define WIDTH 8

module adder (
  input  [`WIDTH-1:0] a, b,
  output [`WIDTH-1:0] y
);
  assign y = a + b;
endmodule

Macros are replaced by the preprocessor before compilation — think of them like #define in C.

🔀 Conditional Compilation

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Useful for enabling debug logic or platform-specific features:

`define DEBUG

module test;
  initial begin
    `ifdef DEBUG
      $display("Debug mode enabled");
    `endif
  end
endmodule

🔄 File Inclusion

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To split code across files:

`include "parameters.vh"

Best practice: Use .vh or .svh extensions for include files.

🚫 Disabling Implicit Nets

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By default, undeclared signals are treated as wire. This can lead to silent bugs. Prevent it using:

`default_nettype none

✅ Best Practices

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• Use `default_nettype none at the top of all files.
• Always wrap macro code with ifdef/endif to avoid naming collisions.
• Avoid overly complex macros — they’re hard to debug.
• Use include only for constants, parameters, or small utility code.