Hierarchical Reference

🧭 Hierarchical Reference

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Hierarchical reference allows accessing signals or instances inside submodules. It’s useful in testbenches, force/release operations, or debugging.

✅ Example:

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top.dut.internal_reg = 8'hA5;  // Accessing signal from testbench

• top: top-level module
• dut: instance name of your DUT
• internal_reg: a signal declared inside dut

⚡ force and release — For Simulation Overrides

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You can override the value of a signal during simulation using force, and restore normal behavior using release.

force top.dut.internal_reg = 8'hFF;  // Override value
#100 release top.dut.internal_reg;   // Return control to simulation

This is useful to:

• Set internal states in testbenches
• Simulate fault injection or error recovery
• Debug hard-to-reach logic

🔧 Use Cases

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• Forcing signal values in simulation
• Observing internal signals not exposed via ports
• Writing testbenches that interact deeply with module internals

⚠️ Avoid using hierarchical references or force/release in synthesizable code — they break module encapsulation and are not synthesizable.