⚙️ Verilog System Functions & Tasks #
Verilog provides many built-in system functions (prefixed with $) to help with simulation, data manipulation, and runtime control. These are not synthesizable and should only be used in testbenches or simulation-only environments.
🎲 Randomization Functions #
| Function | Description | Example |
|---|---|---|
$random |
Returns a 32-bit signed pseudo-random int | r = $random; |
$urandom |
Returns 32-bit unsigned random number | r = $urandom; |
$urandom_range(min, max) |
Bounded unsigned random | r = $urandom_range(0, 15); |
Use for test stimulus generation in testbenches.
🛑 Simulation Control Tasks #
| Task | Description | Example |
|---|---|---|
$stop |
Pauses simulation and enters debugger (if supported) | $stop; |
$finish |
Ends simulation cleanly | $finish; |
$fatal |
Ends simulation with error (like assert) |
$fatal(1, "Error!"); |
➗ Math and Conversion Functions #
| Function | Description | Example |
|---|---|---|
$clog2(x) |
Returns ceiling of log base 2 | localparam W = $clog2(10); |
$bits(x) |
Returns number of bits in variable | $bits(my_reg) |
$signed(x) |
Converts to signed | out = $signed(data); |
$unsigned(x) |
Converts to unsigned | out = $unsigned(signed_data); |
$clog2is useful for parameterizing memory widths, counters, etc.