Delay Controls

⏱️ Delay Controls

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Delay controls simulate time-based or event-driven behavior and are used in testbenches or other non-synthesizable contexts.

🔹 #delay — Time Delay (simulation only)

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#10 a = 1;  // Wait 10 time units before executing

⛔ Not allowed in synthesizable RTL — Using # delays in RTL logic breaks synthesis and must be avoided.

🔹 @event — Event-Based Control

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@(posedge clk) q = d;   // Wait until rising edge of clk
@(a or b) out = a & b;  // Wait until 'a' or 'b' changes

🔹 wait — Blocking Wait Statement

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The wait statement blocks execution until a condition becomes true.

wait (ready == 1);   // Wait until 'ready' is asserted
a = data_in;         // Then execute assignment

🔹 Combined Example

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always @(posedge clk) begin
  wait (ready);       // Wait until 'ready' is high
  a = temp;           // Then assign 'temp' to 'a'
end

repeat with intra-assignment vs regular delay

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🎯 Difference: The first captures b early, the second uses b after the delay.