Verilog Simulation Basics

🧪 Verilog Simulation Basics

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Simulation in Verilog is the process of executing your design over time to observe behavior and verify correctness.

💡 Key Concepts:

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• Simulation time progresses in discrete steps (e.g., #10).
• Testbenches apply inputs and observe outputs.
• No synthesis — purely virtual execution.

🧰 What is a Testbench?

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A testbench is a Verilog module that instantiates the DUT (Design Under Test), generates input stimuli, and optionally monitors outputs.

✅ Example:

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module tb;
  reg clk, rst;
  wire out;

  my_design dut (.clk(clk), .rst(rst), .out(out));

  initial begin
    rst = 1; #5; rst = 0;
    #100 $finish;
  end
endmodule

Testbenches are not synthesizable and often use $display, $monitor, $dumpvars.

⏱️ timescale Directive

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The timescale directive defines simulation time units and precision.

✅ Syntax:

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`timescale 1ns / 1ps

Always place timescale at the top of each .v file, especially testbenches.

🧭 Verilog Simulation Scheduling Regions

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Verilog simulation proceeds in 4-phase cycles every time step:

This order ensures correct execution of <=, $display, and signal transitions.

⏰ Clock Generation in Testbench

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A clock signal can be generated using initial + forever or always.

✅ Example 1: Using always

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reg clk = 0;
always #5 clk = ~clk;  // 10ns clock period

✅ Example 2: Using initial

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initial begin
  clk = 0;
  forever #5 clk = ~clk;
end

Avoid using forever inside synthesizable code — this is testbench only.

🔄 Typical Simulation Flow

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1. initial blocks start at time 0.
2. assign/always logic responds to changes.
3. Time advances using # delays or event triggers.
4. $monitor, $dumpvars record output.

🧪 Behavioral vs Gate-Level Simulation in Verilog

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🔹 Behavioral Simulation

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• Operates at the RTL (Register Transfer Level).
• Describes the intended functionality using always, assign, initial, etc.
• Fast and ideal for early functional testing.
• Does not include actual gate-level structure or delays.

🔹 Gate-Level Simulation

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• Simulates the synthesized netlist — logic gates, flip-flops, muxes, etc.
• Reflects real hardware behavior, including timing delays and fan-out effects.
• Slower, but essential for final verification.
• Includes Standard Delay Format (SDF) files in ASIC flows.