Task and Function

🔧 Task and Function in Verilog

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Tasks and functions are used to avoid code repetition and to encapsulate reusable logic. They improve code readability and maintainability, especially in simulation and testbench designs.

📌 task

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Tasks are procedural blocks that can have:

• Multiple inputs and outputs
• Timing controls like #, @, wait
• Can call other tasks or functions
• Can be used to drive global variables (unless overridden by local declarations)
• Cannot be used inside assign expressions

✅ Example:

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task convert;
  input  [7:0] adc_in;
  output [7:0] out;
  begin
    out = (9/5) * (adc_in + 32);
  end
endtask

🔔 Usage:

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always @(adc_a) convert(adc_a, adc_a_conv);

📌 function

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Functions are pure logic blocks that:

• Must execute in zero simulation time
• Can only return one value
• Cannot include delays (#, @, wait, posedge, etc.)
• Can call other functions, but cannot call tasks
• Can be used in expressions, such as inside assign

✅ Example:

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function [7:0] myfunction;
  input [3:0] a, b, c, d;
  begin
    myfunction = ((a + b) + (c - d));
  end
endfunction

🔔 Usage:

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assign f = myfunction(a, b, c, d) ? e : 8'd0;

🧠 Comparison Table

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⚠️ Best Practices

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• Use task for time-dependent or procedural operations.
• Use function for pure, combinational calculations.