Parameters

🎛️ Parameters in Verilog

#

Parameters are compile-time constants used to make modules configurable and reusable.

✅ Define Inside Module:

#

module counter #(parameter WIDTH = 8) (
  input clk,
  output [WIDTH-1:0] out
);

✅ Override During Instantiation:

#

counter #(.WIDTH(16)) u_counter (
  .clk(clk),
  .out(data)
);

🔒 Local Parameters

#

Use localparam to define constants that cannot be overridden during module instantiation.

module timer;
  localparam TIMEOUT_CYCLES = 100;
endmodule

Useful for internal constants derived from other parameters or used for fixed values.

Key Points:

• Parameters are not variables — they cannot change at runtime.
• Often used to set data widths, address sizes, etc.