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Blocking vs Non-Blocking Assignments

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HDL Verilog HDL
Axolot Logic
Author
Axolot Logic
Digital Design Engineer
Table of Contents
Verilog HDL Series - This article is part of a series.
Part 10: This Article

⛓️ Blocking vs Non-Blocking Assignments in Verilog
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Verilog provides two types of procedural assignments inside always or initial blocks:


➡️ Blocking Assignment (=)
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  • Executes immediately and in sequence
  • Each line blocks the next until it’s done
  • Typically used in combinational logic

✅ Example:
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always @(*) begin
  a = b;
  c = a;  // uses updated 'a'
end

Think: Like normal programming assignments (step-by-step).


Non-Blocking Assignment (<=)
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  • Schedules the update — doesn’t happen immediately
  • Allows all right-hand sides to be evaluated before updating left-hand sides
  • Used in sequential (clocked) logic

✅ Example:
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always @(posedge clk) begin
  a <= b;
  c <= a;  // 'a' is not updated yet, uses old value
end

Think: Like flip-flop behavior — values update at the end of the clock cycle.


🧠 Best Practice
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Context Preferred Assignment
Combinational logic (always @(*)) = (blocking)
Sequential logic (always @(posedge clk)) <= (non-blocking)

Never mix = and <= in the same always block — it can lead to confusing and incorrect simulation behavior.


Verilog HDL Series - This article is part of a series.
Part 10: This Article

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