SystemVerilog Tasks and Functions

🔧 SystemVerilog Tasks and Functions

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SystemVerilog provides tasks and functions to help you write reusable blocks of code. These are used extensively in both RTL modeling and testbench development for calculations, procedural modeling, stimulus generation, and communication between components.

📌 Overview

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🧠 When to Use

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🔁 Function Syntax

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A function returns a single value and completes in zero simulation time.

function int add(int a, int b);
  return a + b;
endfunction

int result = add(3, 5);

• Can’t contain #delay, @, wait, or time-consuming operations
• Must return exactly one value
• All inputs are passed by value

🔄 Task Syntax

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A task can do everything a function can’t — including delays and returning multiple outputs.

task automatic delay_and_add(input int a, b, output int sum);
  #5;
  sum = a + b;
endtask

int x;
delay_and_add(2, 3, x);

• Can use #, @, wait, $display, etc.
• Inputs/outputs can be passed by value, reference, or inout
• Supports zero or more return values

📥 Input, Output, Inout

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task operate(input int a, inout int b, output int result);
  b += a;
  result = a * b;
endtask

🧠 automatic vs static

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By default, tasks and functions in Verilog are static — shared among calls. In SystemVerilog, you can use automatic to allocate separate stack frames per call.

task automatic do_something();
  int counter = 0;
  counter++;
  $display("Counter = %0d", counter);
endtask

✅ Always use automatic for recursive calls, reentrant tasks, or concurrent testbenches.

🧪 Example: Function in RTL Design

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module alu(input logic [3:0] a, b, output logic [4:0] result);

  function logic [4:0] add;
    input logic [3:0] x, y;
    add = x + y;
  endfunction

  assign result = add(a, b);

endmodule

🧪 Example: Task in Testbench

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task automatic print_banner(string msg);
  $display("\n=====================");
  $display("  %s", msg);
  $display("=====================\n");
endtask

initial begin
  print_banner("Simulation Started");
end

🚦 Synthesis vs Simulation

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✅ Best Practices

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• Use functions for combinational, stateless logic
• Use tasks in testbenches for procedural control and time-based actions
• Use automatic to avoid side effects and shared state
• Avoid tasks with delay in synthesizable modules
• Prefer named arguments for clarity:

my_task(.a(10), .b(20), .result(my_var));

🔚 Summary

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SystemVerilog tasks and functions allow you to write modular, reusable, and intent-expressive code — which is critical in both design and verification.