SystemVerilog Loops & Control Flow Statements

🔁 SystemVerilog Loops & Control Flow Statements

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SystemVerilog provides several looping constructs and control flow mechanisms that make it easy to write flexible and dynamic RTL logic and testbench behavior. These constructs resemble those in traditional programming languages like C, but with simulation and hardware modeling in mind.

🔄 Loop Types in SystemVerilog

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1. for Loop

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The most common loop, similar to C-style syntax.

for (int i = 0; i < 10; i++) begin
  $display("i = %0d", i);
end

• Suitable for known iteration counts
• Can declare loop variable inside or outside

2. while Loop

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Executes as long as the condition is true.

int i = 0;
while (i < 5) begin
  $display("i = %0d", i);
  i++;
end

• Use with caution in hardware: avoid unbounded loops in RTL

3. do...while Loop

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Executes at least once, checks condition at the end.

int i = 0;
do begin
  $display("i = %0d", i);
  i++;
end while (i < 3);

• Useful when you want to run the loop body at least once

4. foreach Loop

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Special loop to iterate over arrays (packed, unpacked, dynamic, associative).

int arr[5] = '{0, 1, 2, 3, 4};

foreach (arr[i]) begin
  $display("arr[%0d] = %0d", i, arr[i]);
end

• Simplifies array traversal
• Works well in testbenches

🧭 Control Flow Statements

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break

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Exits the current loop immediately.

for (int i = 0; i < 10; i++) begin
  if (i == 5) break;
  $display("i = %0d", i);
end

💡 Use break when you want to stop iterating under certain conditions.

continue

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Skips the rest of the current iteration and goes to the next.

for (int i = 0; i < 5; i++) begin
  if (i == 2) continue;
  $display("i = %0d", i);
end

💡 Useful to skip unwanted values or conditions.

return

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Used inside a task or function to exit early and optionally return a value.

function int square(int x);
  if (x < 0)
    return 0;
  return x * x;
endfunction

• Not used to exit loops, but to exit functions/tasks

⚠️ Hardware Design Tip

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• Avoid using unbounded while or do...while in synthesizable RTL
• break and continue are not synthesizable in RTL — use FSM logic instead
• These constructs are mainly useful in testbenches, UVM, and behavioral models

✅ Summary Table

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SystemVerilog’s control flow features help create intuitive and flexible logic, especially in testbenches. In synthesizable design, always ensure loops are bounded and deterministic.