Welcome to Axolotl Design & Verification

👋 Welcome!

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Hi there, and welcome to Axolotl Design & Verification – a personal technical blog focused on hardware design, HDL (Hardware Description Languages), and digital verification techniques.

🎯 What is this site about?

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This blog is dedicated to:

• Digital design with Verilog and SystemVerilog
• ASIC & FPGA design flow
• UVM-based verification methodologies
• RISC-V architecture & processor design
• Power-aware and low-power hardware techniques
• Tutorials and guides for beginners & professionals

🧠 Who am I?

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I’m Kerim, a digital IC design and verification engineer with experience in processor microarchitecture, SystemVerilog/UVM verification, and FPGA prototyping. I’m passionate about sharing what I learn and building a community around modern hardware design practices.

📚 What can you expect?

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I’ll regularly publish:

• Step-by-step tutorials for learning Verilog/SystemVerilog
• Deep dives into RISC-V cores and design decisions
• Real-world examples from UVM verification environments
• Power optimization techniques like clock gating
• Testbench patterns, Makefiles, assertions and more

🤝 Let’s Connect

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Feel free to comment, ask questions, or connect with me on GitHub or LinkedIn. I’d love to hear your thoughts and collaborate on exciting ideas.

Stay tuned — more content is coming soon!

💡 “Digital systems are not just built — they’re engineered with clarity and vision.”