RISC-V Imperas

Table of Contents

🧪 Imperas RISC-V Test Framework and riscvOVPsim Simulator
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Imperas’ RISC-V test infrastructure and the riscvOVPsim simulator are essential tools for validating and verifying RISC-V processor compliance. This guide explores what these tools are, how to use them, and how they can be integrated into your own processor development and verification flow.

🔧 What is the Imperas RISC-V Test Framework?
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Imperas provides a test framework designed to check compliance of RISC-V processors with the official Instruction Set Architecture (ISA) specifications.

Actively used by the RISC-V International Compliance Working Group since 2018.
Based on simple make and bash workflows — no complex dependencies.
All you need is to specify a target and test suite to get started.

🔗 GitHub: imperas-riscv-tests

🖥️ What is riscvOVPsim?
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riscvOVPsim is a high-speed simulator that implements full support for both the User and Privileged RISC-V specifications.

Licensed under Apache 2.0 — open-source and free to use.
Ideal for compliance testing and bare-metal software validation.
Advanced commercial features include:
- Variant selection
- Semi-hosting
- Instruction tracing
- Functional coverage reporting
- Signature dump support for RISC-V International test suites

🔗 GitHub: riscv-ovpsim

🧮 riscvOVPsim vs riscvOVPsimPlus
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Feature	`riscvOVPsim`	`riscvOVPsimPlus`
Compliance Testing	✅	✅
Vector/Bitmanip Support	❌	✅ (V, B, K, Zfinx extensions)
GDB/Eclipse Debugging	❌	✅
Multi-Hart / Hypervisor	❌	✅
Instruction Trace	❌	✅ (configurable)

🧪 Test Suites and Integration
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Imperas supports both its own test suites and those provided by the RISC-V Architectural Test SIG (formerly Compliance Task Group).

Unified usage via make/bash interface.
RISC-V International test suites are tagged with -RVI in directory names.
Each simulator/target must be mapped in a riscv-target/ directory.

▶️ Requirements for Running the Tests
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A configured RISC-V toolchain
A suitable simulator (e.g., riscvOVPsim)
Properly defined RISCV_PREFIX and RISCV_TARGET

git clone https://github.com/Imperas/riscv-toolchains.git --branch rvv-0.8.x
mv riscv-toolchains riscv-toolchains-rvv-0.8.x

🧭 Using Imperas RISC-V Tests on Your Own Processor
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This section shows how to run Imperas RISC-V tests on a custom RISC-V processor.

1️⃣ Install Required Tools and Dependencies
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1.1 Install System Dependencies:
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sudo apt-get update
sudo apt-get install -y build-essential gcc g++ make autoconf automake \
libmpc-dev libmpfr-dev libgmp-dev gawk texinfo bison flex device-tree-compiler \
zlib1g-dev libexpat-dev python3 python3-pip

1.2 Build RISC-V Toolchain:
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git clone --recursive https://github.com/riscv/riscv-gnu-toolchain.git
cd riscv-gnu-toolchain
./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d
make -j$(nproc)
sudo make install

Add to your PATH:

echo 'export PATH=/opt/riscv/bin:$PATH' >> ~/.bashrc
source ~/.bashrc

2️⃣ Clone and Build imperas-riscv-tests
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git clone https://github.com/riscv-ovpsim/imperas-riscv-tests.git
cd imperas-riscv-tests

make RISCV_TARGET=my_cpu RISCV_PREFIX=riscv32-unknown-elf-

RISCV_TARGET: a folder under riscv-target for your processor
RISCV_PREFIX: your compiler prefix

Test outputs will be generated in work/<target>/reports

3️⃣ Install OVPSim (Reference Simulator)
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mkdir -p ~/imperas
tar -xvzf imperas.tar.gz -C ~/imperas
echo 'export PATH=~/imperas/bin:$PATH' >> ~/.bashrc
source ~/.bashrc
ovpsim --version

4️⃣ Running the Tests
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4.1 On OVPSim:
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ovpsim --program work/my_cpu/tests/test_program.elf

4.2 On Your Own Processor:
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Convert the ELF to binary:

riscv32-unknown-elf-objcopy -O binary test.elf test.bin

Run via your simulator:

./my_cpu_simulator test.bin

5️⃣ Comparing Results
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ovpsim --program test.elf > ovpsim_output.log
./my_cpu_simulator test.bin > processor_output.log
diff ovpsim_output.log processor_output.log

If there are no differences, the test passed ✅

6️⃣ Troubleshooting Tips
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Problem	Solution
Missing CSR / Unsupported ISA	Verify ISA extensions your CPU supports
Toolchain errors	Rebuild GCC with correct `--with-arch` and `--with-abi`
Makefile issues	Ensure `RISCV_TARGET` directory and configs are correct