🔁 Procedural vs Continuous Assignments in Verilog#
Verilog supports two main types of assignments, each used in different contexts for modeling hardware accurately.
⚙️ Continuous Assignment#
- Uses the
assignkeyword - Automatically updates the output whenever any input changes
- Describes combinational logic
- Signal must be a
wiretype
✅ Example:#
assign y = a & b;
Key Points:
- Declared outside any
alwaysorinitialblock - Suitable for simple logic and dataflow connections
- Behaves like a real physical wire
🔁 Procedural Assignment#
- Defined inside
initialoralwaysblocks - Describes sequential or controlled logic
- Signal must be a
reg,integer, orreal
✅ Example:#
always @(posedge clk) begin
count <= count + 1;
end
Key Points:
- Supports conditional logic (
if,case,for) - Must use
=(blocking) or<=(non-blocking) - Used for FSMs, registers, clocked logic
🧠 Summary Table#
| Feature | Continuous Assignment | Procedural Assignment |
|---|---|---|
| Keyword | assign | always, initial |
| Signal type | wire | reg, integer, etc. |
| Location | Outside blocks | Inside procedural blocks |
| Update timing | Continuous | On triggered events |
| Control structures | ❌ Not supported | ✅ Supported |
| Synthesis use | ✅ Yes | ✅ Yes |
🔍 Tip: Common Error#
reg y;
assign y = a & b; // ❌ Error! Cannot drive reg from assign
➡️ Use wire with assign, or move logic into an always block.
💡 Understanding these two assignment types is essential for writing valid, synthesizable Verilog code.