🧬 Verilog Data Types, Logic Values, Arrays & Net Types#
Verilog provides a variety of data types and signal states for modeling hardware behavior, both in simulation and synthesis. This section covers the most common types, how logic works in 4-state simulation, and how to structure data using arrays and module instances.
📦 Common Verilog Data Types#
Data Type | Default Size | Initial Value | Sign Status | Usage Area | Example Declaration |
---|---|---|---|---|---|
wire | 1 bit | ‘z’ (high impedance) | unsigned | Combinational circuits, module connections | wire [7:0] data_bus; |
reg | 1 bit | ‘x’ (unknown) | unsigned | Sequential circuits, procedural blocks | reg [15:0] counter; |
integer | ≥32 bit | ‘x’ (unknown) | signed | Loop counters, general calculations | integer i; |
real | 64 bit | 0.0 | signed | Floating-point calculations | real voltage; |
time | ≥64 bit | 0 | unsigned | Time values | time current_time; |
parameter | Variable | Defined value | Variable | Constants | parameter WIDTH = 8; |
localparam | Variable | Defined value | Variable | Local constants | localparam DELAY = 10; |
🔢 Verilog Logic Values#
Verilog uses a 4-state logic system where each bit can represent more than just 0 and 1:
Value | Name | Meaning |
---|---|---|
0 | Logic Zero | Driven low (active logic 0) |
1 | Logic One | Driven high (active logic 1) |
x | Unknown | Conflict or uninitialized |
z | High Impedance | Not driven / floating — e.g., tri-state bus |
⚠️
x
andz
values are critical for debugging and modeling bus behavior in simulation.
🧠 Example#
module tb_logic_values;
reg a = 1'b1;
reg b = 1'bz;
reg c = 1'bx;
reg d = 1'b0;
initial begin
$display("a = %b", a);
$display("b = %b", b);
$display("c = %b", c);
$display("d = %b", d);
end
endmodule
a
: logic highb
: high impedance (undriven)c
: unknown due to conflict or missing assignmentd
: logic low
📏 Scalar vs Vector#
🔹 Scalar#
- A single-bit signal (default when no width specified)
wire enable; // 1-bit scalar
🔹 Vector#
- A multi-bit signal — typically used for buses or grouped bits
wire [7:0] data_bus;
reg [3:0] nibble;
📚 Arrays in Verilog#
Arrays enable grouping of signals, memory structures, register files, and multi-instance modules.
🔹 1. Packed Arrays (Bit-Vectors)#
A packed array represents a fixed-width vector.
reg [3:0] my_bus;
Example:#
module tb_bit_select;
reg [3:0] my_bus = 4'b1010;
initial begin
$display("Bit 2: %b", my_bus[2]); // Output: 1
end
endmodule
🔹 2. Unpacked Arrays (Memory Style)#
Used to model RAM, ROM, or lookup tables.
reg [7:0] memory [0:255];
Example:#
module tb_memory_init;
reg [7:0] memory [0:3];
initial begin
memory[0] = 8'hFF;
memory[1] = 8'hA2;
$display("memory[0] = %h", memory[0]);
$display("memory[1] = %h", memory[1]);
end
endmodule
🔹 3. Multidimensional Arrays#
Supported since Verilog-2001. Commonly used in image buffers, matrices, and cache designs.
reg [7:0] image [0:63][0:63]; // 64x64 grid
🔹 4. Array Initialization with Loops#
module tb_memory_clear;
reg [7:0] memory [0:255];
integer i;
initial begin
for (i = 0; i < 256; i = i + 1)
memory[i] = 8'h00;
// Display first few entries for verification
$display("memory[0] = %h", memory[0]);
$display("memory[1] = %h", memory[1]);
$display("memory[255] = %h", memory[255]);
end
endmodule
🔹 5. Array of Module Instances#
Verilog allows generate
blocks to instantiate repeated hardware structures:
module top_module (
input [3:0] in,
output [3:0] out
);
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : gen_block
my_module u_inst (
.in(in[i]),
.out(out[i])
);
end
endgenerate
endmodule
module my_module (
input in,
output out
);
assign out = ~in;
endmodule
🔹 Vector Bit-Select and Part-Select Addressing#
Allows accessing individual bits or ranges (slices) within a vector signal.
module tb_select;
reg [7:0] a = 8'b1101_0110;
initial begin
$display("a = %b", a);
$display("a[3] = %b", a[3]); // Bit-select: accesses bit 3
$display("a[7:4] = %b", a[7:4]); // Part-select: accesses bits 7 down to 4
end
endmodule
Useful for manipulating specific bits of buses or registers.
🔹 Assignments and Truncation#
When assigning between vectors of different widths, extra bits are truncated or padded with zeros.
module tb_truncation_padding;
reg [7:0] a;
reg [3:0] b;
initial begin
b = 4'b1011;
a = b; // Zero-padded to 8 bits
$display("a = %b", a); // Expected: 00001011
a = 8'b11011010;
b = a; // Truncated to lower 4 bits
$display("b = %b", b); // Expected: 1010
end
endmodule
Truncation can lead to data loss if not handled carefully.
🎯 Array Types Summary#
Array Type | Description | Use Case |
---|---|---|
Packed Array | Bit-vectors | Ports, buses, logic operations |
Unpacked Array | Indexed storage of elements | RAM, register file |
Multidimensional Array | Matrix of elements | Caches, images, framebuffers |
Array of Instances | Multiple module instantiations | Pipelining, parallel structures |