📉 VCD – Value Change Dump#
VCD (Value Change Dump) is a standard waveform file format generated during Verilog simulation. It records signal transitions over time, which can be viewed in tools like GTKWave.
✅ How to Generate VCD:#
Inside your testbench:
initial begin
$dumpfile("wave.vcd"); // Output file name
$dumpvars(0, tb_top); // Dump all signals in tb_top hierarchy
end
$dumpfile: sets the filename.$dumpvars(level, scope): sets how many levels of signals to record.
📊 View with GTKWave:#
gtkwave wave.vcd
💡 Additional VCD Tasks#
| Task | Description |
|---|---|
$dumpfile | Sets the name of the output VCD file |
$dumpvars | Starts recording value changes |
$dumpoff | Temporarily disables dumping |
$dumpon | Resumes dumping |
$dumpall | Forces all current values to dump |
$dumpflush | Flushes data to file immediately |
$dumpports | Dumps only port-level signals |
✅ Summary#
| Concept | Purpose | Used in |
|---|---|---|
| Namespace | Limits scope of identifiers | Modules |
| VCD | Stores signal changes for waveform view | Testbenches |
$dumpfile | Sets VCD output file | Simulation |
$dumpvars | Starts signal recording | Simulation |
module tb_vcd_demo;
reg clk = 0;
reg rst = 1;
reg [3:0] counter = 0;
// Clock generation
always #5 clk = ~clk;
// Simple counter logic
always @(posedge clk) begin
if (rst)
counter <= 0;
else
counter <= counter + 1;
end
// VCD dump setup
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, tb_vcd_demo);
#10 rst = 0;
#100 $finish;
end
endmodule