Verilog Namespaces: Understanding Scope and Modularity

🌐 Verilog Namespaces

#

Verilog uses a flat, module-based namespace. This means:

• Identifiers must be unique within a given scope (e.g., inside a module).

• Modules themselves form separate namespaces.

• Inside a module, you can have:

  • Local variables
  • Ports
  • Internal wires and regs

• No nested functions, no packages like SystemVerilog — limited modularity.

🧠 Example:

#

module ALU;
  reg [3:0] result;   // Only visible inside this module
endmodule

module top;
  wire [3:0] result;  // This is a different 'result'
endmodule

If two modules both have result, they are independent unless explicitly connected via ports.