📥 Command-Line Input in Verilog#
In Verilog testbenches, accepting command-line arguments makes your simulations parameterizable and reusable. This is especially useful for passing different seed, mode, or testcase values without modifying the testbench code.
🔹 $value$plusargs#
Used to capture arguments with values, passed in the form +ARG=VALUE.
$value$plusargs("SEED=%d", seed);
This call returns 1 and assigns the value to seed if +SEED=123 is passed at runtime. Otherwise, it returns 0.
✅ Example:#
integer seed;
initial begin
if (!$value$plusargs("SEED=%d", seed)) begin
seed = 42; // Default fallback
end
$display("Using seed: %0d", seed);
end
🔹 $test$plusargs#
Checks for the presence of a flag (boolean-style argument) without an associated value.
if ($test$plusargs("VERBOSE")) begin
$display("Verbose mode is ON.");
end
Returns 1 if +VERBOSE was passed, otherwise 0.
🖥️ Simulation Command#
vvp a.out +SEED=123 +VERBOSE
🧠 Summary Table#
| Category | Function | Description |
|---|---|---|
| Value input | $value$plusargs("FORMAT", var) | Retrieves and assigns value |
| Flag detection | $test$plusargs("NAME") | Checks if flag is present |
module tb_cmd_args;
integer seed;
bit verbose;
initial begin
// Get numeric seed from command line
if (!$value$plusargs("SEED=%d", seed)) begin
seed = 0; // Default seed
end
// Check for +VERBOSE flag
if ($test$plusargs("VERBOSE")) begin
verbose = 1;
$display("Verbose mode is ON.");
end else begin
verbose = 0;
end
$display("Simulation Seed = %0d", seed);
#10 $finish;
end
endmodule