Verilog Hierarchical Reference: Accessing Internal Signals

🧭 Hierarchical Reference

#

Hierarchical reference allows accessing signals or instances inside submodules. It’s useful in testbenches, force/release operations, or debugging.

✅ Example:

#

top.dut.internal_reg = 8'hA5;  // Accessing signal from testbench

• top: top-level module
• dut: instance name of your DUT
• internal_reg: a signal declared inside dut

⚡ force and release — For Simulation Overrides

#

You can override the value of a signal during simulation using force, and restore normal behavior using release.

force top.dut.internal_reg = 8'hFF;  // Override value
#100 release top.dut.internal_reg;   // Return control to simulation

This is useful to:

• Set internal states in testbenches
• Simulate fault injection or error recovery
• Debug hard-to-reach logic

🔧 Use Cases

#

• Forcing signal values in simulation
• Observing internal signals not exposed via ports
• Writing testbenches that interact deeply with module internals

⚠️ Avoid using hierarchical references or force/release in synthesizable code — they break module encapsulation and are not synthesizable.

module top;
    dut u_dut();  // Instantiate DUT
endmodule

module dut;
    reg [7:0] internal_reg = 8'h00;
endmodule

module tb_hierarchical_ref;

    initial begin
        // Set internal signal using hierarchical reference
        force top.u_dut.internal_reg = 8'hFF;
        #10;
        $display("Forced value = %h", top.u_dut.internal_reg);

        // Release the override
        release top.u_dut.internal_reg;
        #10;
        $display("Released value = %h", top.u_dut.internal_reg);

        $finish;
    end

endmodule