⏱️ Delay Controls#
Delay controls simulate time-based or event-driven behavior and are used in testbenches or other non-synthesizable contexts.
🔹 #delay — Time Delay (simulation only)#
#10 a = 1; // Wait 10 time units before executing
⛔ Not allowed in synthesizable RTL — Using
#delays in RTL logic breaks synthesis and must be avoided.
🔹 @event — Event-Based Control#
@(posedge clk) q = d; // Wait until rising edge of clk
@(a or b) out = a & b; // Wait until 'a' or 'b' changes
🔹 wait — Blocking Wait Statement#
The wait statement blocks execution until a condition becomes true.
wait (ready == 1); // Wait until 'ready' is asserted
a = data_in; // Then execute assignment
🔹 Combined Example#
always @(posedge clk) begin
wait (ready); // Wait until 'ready' is high
a = temp; // Then assign 'temp' to 'a'
end
repeat with intra-assignment vs regular delay#
| Syntax | Meaning |
|---|---|
a = repeat(3) @(posedge clk) b; | Captures b immediately, then waits 3 rising edges before assigning to a. |
repeat(3) @(posedge clk); a = b; | Waits for 3 rising edges, then assigns current value of b to a. |
🎯 Difference: The first captures
bearly, the second usesbafter the delay.
module tb_delay_control;
reg clk = 0;
reg ready = 0;
reg [7:0] data_in = 8'hA5, temp = 8'h3C, a, b;
// Clock generation
always #5 clk = ~clk;
// Time delay example
initial begin
#10 b = 8'hF0;
end
// Event and wait example
always @(posedge clk) begin
wait (ready == 1);
a = temp;
end
// Trigger ready after 3 cycles
initial begin
#30 ready = 1;
#50;
$stop;
end
// repeat vs delay assignment
initial begin
b = 0;
repeat(3) @(posedge clk); // delay for 3 cycles
b = data_in;
end
endmodule