⛓️ Blocking vs Non-Blocking Assignments in Verilog#
Verilog provides two types of procedural assignments inside always or initial blocks:
➡️ Blocking Assignment (=)#
- Executes immediately and in sequence
- Each line blocks the next until it’s done
- Typically used in combinational logic
✅ Example:#
always @(*) begin
a = b;
c = a; // uses updated 'a'
end
Think: Like normal programming assignments (step-by-step).
⏩ Non-Blocking Assignment (<=)#
- Schedules the update — doesn’t happen immediately
- Allows all right-hand sides to be evaluated before updating left-hand sides
- Used in sequential (clocked) logic
✅ Example:#
always @(posedge clk) begin
a <= b;
c <= a; // 'a' is not updated yet, uses old value
end
Think: Like flip-flop behavior — values update at the end of the clock cycle.
🧠 Best Practice#
| Context | Preferred Assignment |
|---|---|
Combinational logic (always @(*)) | = (blocking) |
Sequential logic (always @(posedge clk)) | <= (non-blocking) |
❗ Never mix
=and<=in the samealwaysblock — it can lead to confusing and incorrect simulation behavior.