Verilog
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Introduction to Verilog: Basics for Digital Design
·1176 words·6 mins·
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Kerim Turak
Hardware Design
Verilog
FPGA
ASIC
RTL Design
Hardware Description Language
Hardware Design
Verilog Design Methodologies & Modeling Styles
·473 words·3 mins·
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Kerim Turak
Hardware Design
Verilog
Design Methodology
RTL Modeling
Hardware Design
Digital Design Flow
Hardware Design
Hardware Design Abstraction Levels in Verilog
·238 words·2 mins·
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Kerim Turak
Hardware Design
Hardware Abstraction
RTL Design
Gate Level
Transistor Level
Digital Design
Hardware Design
Verilog Data Types, Logic Values & Arrays Explained
·747 words·4 mins·
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Kerim Turak
Hardware Design
Verilog Data Types
Verilog Logic
Verilog Arrays
HDL Modeling
Digital Design
Hardware Design
Verilog Modules, Ports, Assignments & Best Practices
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Kerim Turak
Hardware Design
Verilog Module
Verilog Ports
Verilog Assign
Verilog Always
Hardware Description Language
Hardware Design
Verilog initial Block: Testbench & Simulation Essentials
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Kerim Turak
Hardware Design
Verilog Initial
Verilog Testbench
Simulation
Hardware Verification
Digital Design
Hardware Design
Verilog Control Flow: if, case, loops & RTL Guidelines
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Kerim Turak
Hardware Design
Verilog Control Flow
Verilog If-Else
Verilog Case
Verilog Loops
RTL Design
Hardware Design
Verilog generate Block: Parameterized Hardware Design
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Kerim Turak
Hardware Design
Verilog Generate
Parameterized Design
RTL Design
Hardware Synthesis
Digital Design
Hardware Design
Verilog Assignments: Procedural vs. Continuous Explained
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Kerim Turak
Hardware Design
Verilog Assignments
Continuous Assignment
Procedural Assignment
RTL Design
Hardware Description Language
Hardware Design
Verilog Blocking vs. Non-Blocking Assignments
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Kerim Turak
Hardware Design
Verilog Assignments
Blocking Assignment
NonBlocking Assignment
RTL Design
Sequential Logic
Hardware Design
Verilog Syntax Overview: Essentials for Digital Design
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Kerim Turak
Hardware Design
Verilog Syntax
Verilog Basics
Data Types
RTL Coding
Hardware Description Language
Hardware Design
Verilog Parameters: Making Modules Reusable & Configurable
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Kerim Turak
Hardware Design
Verilog Parameters
Reusable Design
Configurable Modules
RTL Design
Hardware Description Language
Hardware Design
Verilog Task vs. Function: Reusable Logic in HDL
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Kerim Turak
Hardware Design
Verilog Task
Verilog Function
Reusable Code
HDL Coding
Testbench Design
Hardware Design
Verilog Simulation Basics & Testbench Design
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Kerim Turak
Hardware Design
Verilog Simulation
Testbench
Timescale
Simulation Regions
Hardware Verification
Hardware Design
Verilog Delay Controls: #Delay, @Event, Wait
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Kerim Turak
Hardware Design
Verilog Delay
Event Control
Wait Statement
Simulation
Testbench
Hardware Design
Verilog System Functions & Tasks for Simulation
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Kerim Turak
Hardware Design
Verilog System Functions
Verilog Tasks
Simulation
Testbench
Randomization
Hardware Design
Verilog Hierarchical Reference: Accessing Internal Signals
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Kerim Turak
Hardware Design
Verilog Hierarchical Reference
Force Release
Testbench
Simulation Debugging
Hardware Verification
Hardware Design
Verilog Synthesis: From RTL to Gate-Level Netlist
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Kerim Turak
Hardware Design
Verilog Synthesis
RTL Design
Gate Level Netlist
FPGA Design
ASIC Design
Hardware Design
Verilog Compiler Directives & Macros: Conditional Compilation & Code Reuse
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Kerim Turak
Hardware Design
Verilog Directives
Verilog Macros
Conditional Compilation
Code Reuse
Hardware Description Language
Hardware Design
Verilog Command-Line Input: $plusargs for Testbench Control
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Kerim Turak
Hardware Design
Verilog Command Line
Plusargs
Testbench
Simulation Control
Hardware Verification
Hardware Design
Verilog Namespaces: Understanding Scope and Modularity
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Kerim Turak
Hardware Design
Verilog Namespace
Verilog Scope
Modularity
RTL Design
Hardware Description Language
Hardware Design
Verilog VCD: Waveform Dumping for Simulation Analysis
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Kerim Turak
Hardware Design
Verilog VCD
Waveform Viewing
Simulation Analysis
Testbench
GTKWave
Hardware Design
Verilog RTL Design & Testbench Best Practices
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Kerim Turak
Hardware Design
Verilog RTL
RTL Design Rules
Verilog Testbench
Hardware Design Best Practices
Synthesizable Verilog
Hardware Design