📚 Connecting the UVM RAL Model to the Sequencer and Monitor#
When verifying a register model using the UVM Register Abstraction Layer (RAL), it’s crucial that the model can direct read/write requests properly through the bus and also capture register changes initiated by the design. By integrating the RAL model with a sequencer and monitor, you can effectively control both frontdoor and backdoor access.
This page explains how to connect the RAL model to the sequencer and monitor, and how this connection works.
🔗 1️⃣ Connecting to the Sequencer#
🛠️ Why Is It Needed?#
For frontdoor access (reading/writing registers via the bus), the RAL model must be connected to a sequencer. This ensures:
- When making calls like
regmodel.reg.write()orregmodel.reg.read(), the RAL model creates a sequence item through the adapter. - This item is sent to the driver via the sequencer and reaches the design using the bus protocol.
📌 How to Do It#
Example:
// The adapter and sequencer should already be instantiated
regmodel.default_map.set_sequencer(my_sequencer, my_adapter);
default_map: Represents the default address map within the register block.my_sequencer: The sequencer managing bus transactions in the testbench.my_adapter: The adapter class that converts RAL calls into bus protocol transactions.
This connection allows the RAL to direct frontdoor operations to the bus driver.
🔎 2️⃣ Connecting to the Monitor#
🛠️ Why Is It Needed?#
Any register operations performed by the design (or by another master) should also be captured by the testbench. This keeps the RAL model synchronized with the design. These transactions are usually captured by a monitor and sent to the RAL model via a predictor component.
📌 How to Do It#
The monitor typically connects to the predictor using an analysis port:
// Connect the monitor’s analysis port to the predictor’s bus_in port
my_monitor.ap.connect(my_predictor.bus_in);
my_monitor: Listens for bus operations and sends them to the analysis port.my_predictor: Receives bus transactions and performs predictions on the RAL model.
This setup allows: 1️⃣ Frontdoor operations initiated by the driver to go to the RAL model via the sequencer. 2️⃣ The monitor to listen to bus operations and send them to the predictor. 3️⃣ The predictor to update the RAL model.
🔌 3️⃣ The Role of the Adapter#
The adapter bridges the register model and the bus protocol:
reg2bus(): Converts a RAL operation (read/write) into a bus protocol transaction.bus2reg(): Converts the bus response back into the RAL model.
This is critical in the sequencer connection because it translates between the RAL model’s register operations and the bus protocol.
📝 4️⃣ Connection Flow#
| Step | Description |
|---|---|
| 1️⃣ | The RAL model initiates a register operation (read(), write()). |
| 2️⃣ | The adapter converts the RAL operation into a bus item (reg2bus()). |
| 3️⃣ | The bus item is sent to the driver via the sequencer. |
| 4️⃣ | The driver accesses the design and performs the operation. |
| 5️⃣ | The monitor listens to the bus and sends the transaction to the predictor via the analysis port. |
| 6️⃣ | The predictor receives the bus item from the analysis port. |
| 7️⃣ | The predictor performs a prediction on the RAL model. |
| 8️⃣ | The RAL model is synchronized with the design data. |
📦 5️⃣ Code Examples#
🔹 Connecting to the sequencer:
regmodel.default_map.set_sequencer(my_sequencer, my_adapter);
🔹 Connecting the monitor and predictor:
my_monitor.ap.connect(my_predictor.bus_in);
my_predictor.map = regmodel.default_map;
✨ Summary#
✅ Sequencer Connection: Connects the RAL model to the bus sequencer and adapter for frontdoor access. ✅ Monitor and Predictor Connection: Captures register changes from the design and updates the RAL model. ✅ Adapter: Acts as a bridge between the RAL model and the bus protocol. ✅ Predictor: Updates the register model with transactions captured by the monitor, keeping it synchronized with the design.