UVM RAL: Memory, Address Map, and More

📚 UVM RAL Sections: Memory, Address Map, and More

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The UVM Register Abstraction Layer (RAL) enables high-level modeling and verification of the register structures in a design. These structures are the fundamental building blocks that make up RAL’s hierarchical model. Let’s break them down one by one:

🗂️ 1. Memory

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Memory represents RAM, ROM, or other memory blocks in the design. These blocks can be single- or multi-dimensional. In RAL, they are modeled using the uvm_mem class.

• Features:

  • Address range, word width, and access types can be defined.
  • Can be tested via frontdoor (through the bus) or backdoor (direct HDL access).

• Usage:

  • Access memory using functions like uvm_mem::write() and uvm_mem::read().
  • Typically used to verify DMA, buffer, or FIFO structures.

🗺️ 2. Address Map

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Address Map represents the physical addresses of registers and memory blocks in the design. Modeled with the uvm_reg_map class.

• Features:

  • Stores base address and offset information for each register or memory.
  • Supports addressability depending on bus protocol (byte-addressable or word-addressable).

• Usage:

  • Registers or memory objects in a uvm_reg_block are exposed to the testbench via the map.
  • Used in frontdoor access to communicate with driver/sequencer.

🧩 3. Register Blocks

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A Register Block is a logical grouping of one or more registers and/or memory objects. Modeled with the uvm_reg_block class.

• Features:

  • Typically represents the complete register map of an IP or subsystem.
  • Can build hierarchical structures (block within a block).

• Usage:

  • Separate register blocks can be defined for different design modules (e.g., PCIe_Block, UART_Block).
  • All blocks can be combined under a single top-level block.

📂 4. Register Files

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A Register File is typically used when the same type of register is repeated in a structure. Modeled with the uvm_reg_file class.

• Features:

  • Organizes multiple register objects (e.g., a FIFO pointer register file).
  • Allows indexed access.

• Usage:

  • Access specific registers within the file using syntax like reg_file[3].write(status, value);.

📝 5. Registers

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A Register represents individual registers or multi-bit registers in the design. Modeled with the uvm_reg class.

• Features:

  • Parameters like address, reset value, and access type (RO, RW) can be defined.
  • Supports randomization and coverage.

• Usage:

  • reg_model.my_reg.write(status, 32'hDEADBEEF);
  • reg_model.my_reg.read(status, read_value);

🔑 6. Register Fields

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A Register Field represents bit fields inside a register. Modeled with the uvm_reg_field class.

• Features:

  • Bit position, width, and access type can be defined.
  • Field-level randomization is supported.

• Usage:

  • reg_model.my_reg.my_field.set(3'b101);
  • reg_model.my_reg.my_field.get(value);

✨ Summary

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All of these structures come together in the hierarchical RAL model to offer an easily controllable, randomizable, and verifiable representation of even the most complex designs.