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UVM Sequence Starting Methods

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Education UVM Verification UVM Verification SystemVerilog Sequence Starting Objection Usage
Education UVM Verification
Axolot Logic
Author
Axolot Logic
Digital Design Engineer
Table of Contents
UVM Series - This article is part of a series.
Part 24: This Article

🔍 Introduction
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A UVM Sequence is a fundamental building block for generating stimulus in a testbench. Starting a sequence and controlling its flow is key to writing flexible and reusable testbenches. This page explains the uvm_do macro and alternative ways to start a sequence, including where to raise objections and how to manually implement the steps that uvm_do performs behind the scenes.


🚀 Sequence Starting Methods
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1️⃣ Using uvm_do Macro
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The most common and convenient way in UVM:

`uvm_do(seq_item)

This macro effectively does:

  1. Calls create() to instantiate the sequence item.
  2. Calls randomize() to apply constraints (if any).
  3. Calls start_item() to begin the transaction.
  4. Calls finish_item() to finalize it.

👉 In other words, uvm_do creates and sends the item in a single line.


2️⃣ Manual Sequence Starting (Step-by-Step)
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If you don’t want to use uvm_do or need finer control, you can manually write the steps:

my_item item;
item = my_item::type_id::create("item");

// Randomization (add constraints if needed)
if (!item.randomize())
  `uvm_error("MY_SEQ", "Randomization failed")

// Start the item
start_item(item);

// (Optional) Fill in the fields manually
item.data = 8'hFF;

// Finish the item
finish_item(item);

This is especially useful when you want to set certain fields manually or apply custom constraints.


3️⃣ Starting a Sequence via Sequencer
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You can also start a sequence by explicitly calling start() on the sequencer:

my_sequence seq;
seq = my_sequence::type_id::create("seq");
seq.start(my_sequencer);

This approach is typically used for nested sequences or more complex flows.


🛠️ Using uvm_send
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The uvm_send macro is used to send single sequence items inside a sequence:

`uvm_send(item)

Behind the scenes, this does:

  • start_item(item)
  • (optional randomization or manual field setting)
  • finish_item(item)

all in one step.


📌 Objection Usage
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In UVM, it’s common to raise an objection to prevent the simulation from ending while a sequence is running. Typically done in:

  • start_of_simulation_phase
  • run_phase
  • main_phase

Example:

phase.raise_objection(this, "My sequence started");
...
phase.drop_objection(this, "My sequence completed");

💡 Note: You can raise objections inside the sequence itself or inside the test. This controls when the simulation ends.


🎯 When to Use Each Method?
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MethodWhen to Use
uvm_doSimple stimulus flows, rapid development
Manual (Step-by-Step)When you need manual field assignment or apply special constraints
Sequencer start()Nested sequences or complex control
uvm_sendQuick send of single items

📝 Conclusion
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UVM Sequence starting methods add flexibility and control to your verification environment. Macros like uvm_do are great for rapid development, while manual methods provide more customization. Choose the best method based on your testbench needs and flow control.


UVM Series - This article is part of a series.
Part 24: This Article

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