🛠️ UVM Testbench Top#
🎯 Purpose#
This page explains the top module for the Adder design’s testbench. This module:
✅ Generates clock and reset ✅ Instantiates the Adder DUT ✅ Sets the virtual interface using the UVM config database ✅ Starts the UVM test ✅ Initiates waveform recording
📜 Code Example#
module top;
import adder_pkg::*;
import uvm_pkg::*;
adder_if vif();
adder DUT (
.clk(vif.clk),
.rst(vif.rst),
.num1(vif.num1),
.num2(vif.num2),
.out(vif.out)
);
initial begin
uvm_config_db #(virtual adder_if)::set(null, "*", "vif", vif);
uvm_top.enable_print_topology = 1;
run_test("adder_test");
end
// Clock generation
always #5 vif.clk = ~vif.clk;
initial vif.clk = 0;
// Reset generation
initial begin
vif.rst = 1;
#20 vif.rst = 0;
end
endmodule
🔍 Explanations#
✅ adder_if: The interface that drives data to the Adder DUT and connects the virtual interface to the UVM testbench.
✅ uvm_config_db: Used to assign the virtual interface to UVM components.
✅ run_test(“adder_test”): Starts the test named adder_test.
✅ $dumpfile() and $dumpvars(): Enable waveform recording during simulation.
💡 Summary#
- This top module is the entry point of the UVM testbench.
- All signals and reset are controlled here.
- The virtual interface connection allows the driver and monitor components to communicate with the DUT.
- The default test scenario is
adder_test. - Waveform recording simplifies simulation analysis. 📈