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UVM Environment Usage and adder_env Example

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Education UVM Verification UVM Verification SystemVerilog Uvm_env Testbench Structure
Education UVM Verification
Axolot Logic
Author
Axolot Logic
Digital Design Engineer
Table of Contents
UVM Series - This article is part of a series.
Part 18: This Article

🏗️ UVM Environment: adder_env Example
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🚀 Introduction
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In UVM, the environment is a high-level container that groups together agents, scoreboards, and other verification components. It organizes the testbench structure, manages the connections between components, and often represents a reusable verification environment.


📝 adder_env Example
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Below is a simple adder_env example that demonstrates how an agent and a scoreboard are instantiated and connected.

class adder_env extends uvm_env;
    adder_agent agent;
    adder_subscriber subscriber;
    adder_scoreboard scoreboard;

    `uvm_component_utils(adder_env)

    function new(string name = "adder_env", uvm_component parent);
      super.new(name, parent);
    endfunction

    virtual function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      agent = adder_agent::type_id::create("agent", this);
      subscriber = adder_subscriber::type_id::create("subscriber", this);
      scoreboard = adder_scoreboard::type_id::create("scoreboard", this);
    endfunction

    virtual function void connect_phase(uvm_phase phase);
      super.connect_phase(phase);
      agent.monitor.analysis_port.connect(subscriber.analysis_export); // Subscriber connection
      agent.monitor.analysis_port.connect(scoreboard.analysis_export); // Scoreboard connection
    endfunction
  endclass

🔍 Explanation
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  • agent: The adder_agent instance that contains the sequencer, driver, and monitor.
  • scoreboard: The adder_scoreboard instance that compares the DUT’s output with expected results.
  • build_phase(): Instantiates the agent and scoreboard.
  • connect_phase(): Connects the monitor’s analysis port to the scoreboard’s analysis implementation.
  • start_of_simulation_phase(): Prints a start-of-simulation message for logging and debugging.

💡 Summary
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🔹 The environment groups together verification components to form a modular testbench structure. 🔹 It instantiates agents, scoreboards, and other components and connects them in the connect_phase(). 🔹 A well-structured environment improves testbench reusability, scalability, and maintainability.


UVM Series - This article is part of a series.
Part 18: This Article

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