🤖 UVM Agent Usage and Adder Example#
🚀 Introduction#
In UVM, the uvm_agent is one of the most fundamental building blocks of the testbench. An agent combines the driver, monitor, and sequencer components into a single reusable unit, creating a self-contained verification sub-environment.
An agent can operate in active mode (stimulus generation) or passive mode (monitoring only).
🗂️ What is uvm_agent?#
- The
uvm_agentgroups together the driver, monitor, and sequencer components. - In active mode (
UVM_ACTIVE), the sequencer and driver generate stimulus. - In passive mode (
UVM_PASSIVE), only the monitor is instantiated and runs. - This structure enhances reusability and scalability.
- Agents form the foundation of reusable and parametric UVCs.
📝 Adder Agent Example#
Below is a simple adder_agent example. In active mode, both the driver and sequencer are created, while the monitor is always instantiated.
class adder_agent extends uvm_agent;
adder_driver driver;
adder_monitor monitor;
uvm_sequencer #(adder_transaction) sequencer;
adder_config cfg;
`uvm_component_utils(adder_agent)
function new(string name = "adder_agent", uvm_component parent);
super.new(name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
driver = adder_driver::type_id::create("driver", this);
monitor = adder_monitor::type_id::create("monitor", this);
sequencer = uvm_sequencer #(adder_transaction)::type_id::create("sequencer", this);
if (!uvm_config_db #(adder_config)::get(this, "", "cfg", cfg))
`uvm_fatal("AGENT", "No config specified for the agent!")
endfunction
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
driver.seq_item_port.connect(sequencer.seq_item_export);
endfunction
endclass
🔍 Explanations#
- monitor: Always created to collect DUT data.
- driver and sequencer: Created only in ACTIVE mode (
is_active == UVM_ACTIVE) to generate stimulus. - build_phase(): Where all subcomponents are instantiated.
- connect_phase(): Connects the sequencer to the driver via the TLM port.
- start_of_simulation_phase(): Prints an informational message at the start of the simulation.
💡 Summary#
🔹 The uvm_agent integrates the driver, sequencer, and monitor into a modular structure.
🔹 Supports both active and passive modes, enabling different use cases.
🔹 In the adder example, the agent generates stimulus and observes results for a simple addition operation.
🔹 The agent structure is the foundation for reusable and scalable testbench architectures.