UVM Monitor Usage and Adder Example

🔎 UVM Monitor Usage and Adder Example

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🚀 Introduction

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The uvm_monitor is a key component in a UVM testbench, responsible for observing signals and data flowing through the DUT (Design Under Test). Unlike drivers, monitors do not generate stimuli; instead, they passively capture data from the DUT and forward it to other components—such as coverage collectors or scoreboards—using an analysis port.

🗂️ What is uvm_monitor?

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• The uvm_monitor reads DUT signals and converts them into transaction objects.
• It sends the captured data to other testbench components using an analysis port.
• It uses a virtual interface to connect to DUT signals.
• It plays a crucial role in ensuring coverage and debugging the testbench behavior.

📝 Adder Monitor Example

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Below is an adder_monitor example. This monitor reads DUT inputs and output through the adder_if virtual interface and sends the captured data as adder_transaction objects through the analysis port.

class adder_monitor extends uvm_monitor;
  `uvm_component_utils(adder_monitor)

  virtual adder_if vif;
  uvm_analysis_port #(adder_transaction) analysis_port;

  function new(string name = "adder_monitor", uvm_component parent);
    super.new(name, parent);
    analysis_port = new("analysis_port", this);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if (!uvm_config_db#(virtual adder_if)::get(this, "", "vif", vif))
      `uvm_fatal("NO_VIF", "Virtual interface not set for adder_monitor!")
  endfunction

  virtual task run_phase(uvm_phase phase);
    adder_transaction tr;
    forever begin
      tr = adder_transaction::type_id::create("tr");

      @(posedge vif.clk);
      tr.num1 = vif.num1;
      tr.num2 = vif.num2;

      @(posedge vif.clk);
      tr.result = vif.out;

      // Send the transaction through the analysis port
      analysis_port.write(tr);

      // Print the transaction
      `uvm_info(get_type_name(), $sformatf("Transaction: num1=%0d, num2=%0d, result=%0d", tr.num1, tr.num2, tr.result), UVM_MEDIUM);
    end
  endtask

endclass

🔍 Explanations

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• Virtual Interface (vif): Connects the monitor to the DUT clock and data ports.

• analysis_port: Forwards captured data to components like scoreboards or coverage collectors.

• build_phase(): Retrieves and binds the virtual interface using uvm_config_db.

• run_phase():

  • Reads DUT inputs (num1, num2) and output (out).
  • Sends the transaction to other components using analysis_port.write().
  • Prints the transaction details using uvm_info().

💡 Summary

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🔹 The uvm_monitor passively captures data from the DUT and makes it available to other testbench components. 🔹 Using an analysis port, the captured data can be processed by scoreboards or coverage collectors. 🔹 In this adder example, DUT addition inputs and output are captured and forwarded to the testbench. 🔹 Monitors are essential for building a robust and traceable testbench environment.