📚 What is a UVM Sequencer?

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A UVM sequencer is a component in a testbench that manages and controls the flow of sequence items to the driver. It acts as a mediator between sequences and the driver, ensuring items are sent in an orderly and synchronized fashion.

🔎 Key Responsibilities of the Sequencer

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✅ Receives sequence items and sends them to the driver sequentially.
✅ Performs arbitration to decide which sequence can send items to the driver.
✅ Manages handshaking with the driver (start and finish protocol).
✅ Transfers sequence items to the driver using the start_item() and finish_item() mechanism.

📦 Usage

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In UVM, a sequencer is typically defined like this:

class my_sequencer extends uvm_sequencer #(my_packet);
  `uvm_component_utils(my_sequencer)

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction
endclass

• The base class is parameterized:

  class uvm_sequencer #(type REQ = uvm_sequence_item, RSP = REQ)
    extends uvm_sequencer_param_base #(REQ, RSP);
  

  Typically:

  • REQ = the item type sent to the driver
  • RSP = the response type (default: REQ)

🧩 Example: adder_sequencer

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Here’s an example of a simple adder sequencer:

class adder_sequencer extends uvm_sequencer #(adder_packet);

  `uvm_component_utils(adder_sequencer)

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction

  function void start_of_simulation_phase(uvm_phase phase);
    `uvm_info(get_type_name(),
              {"start of simulation for ", get_full_name()},
              UVM_HIGH)
  endfunction

endclass : adder_sequencer

✅ This sequencer:

• Handles items of type adder_packet.
• Prints a log message at the start of the simulation using start_of_simulation_phase().

📝 Notes:

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• The sequencer does not directly drive signals; it coordinates with the driver through a virtual interface.
• Typically, the sequencer is instantiated inside an agent alongside the driver and monitor.