Skip to main content

UVM Sequence Usage and Adder Example

· loading · loading · ·
Education UVM Verification UVM Verification SystemVerilog Uvm_sequence Stimulus Generation
Education UVM Verification
Axolot Logic
Author
Axolot Logic
Digital Design Engineer
Table of Contents
UVM Series - This article is part of a series.
Part 12: This Article

🎯 UVM Sequence Usage and Adder Example
#

🚀 Introduction
#

The uvm_sequence is one of the core classes used for stimulus (test data) generation in UVM verification environments. It works alongside the sequencer and driver components to create and send transactions.

A UVM testbench is typically built around the sequence, sequencer, and driver triangle. This structure enables modular, reusable, and flexible test scenario development.


🗂️ What is uvm_sequence?
#

The uvm_sequence generates transactions derived from uvm_sequence_item and sends them to the sequencer, which in turn passes them to the driver.
This structure simplifies the organization of test scenarios, data flows, and stimulus generation.

Key Features
#

✅ Generates stimulus by randomizing uvm_sequence_item objects
✅ Defines the main test flow in the body() method
✅ Offers user customization through the pre_body() and post_body() methods
✅ Integrates seamlessly with the sequencer and driver


📝 Adder Sequence Example
#

Below is a simple adder_base_seq example that generates random adder_packet items to test an adder design.

  class adder_sequence extends uvm_sequence #(adder_transaction);
    int num_transactions = 20;

    `uvm_object_utils(adder_sequence)

    function new(string name = "adder_sequence");
      super.new(name);
    endfunction

    virtual task body();
      adder_transaction tr;
      repeat(num_transactions) begin
        tr = adder_transaction::type_id::create("tr");
        `uvm_do(tr);
      end
    endtask

/*
  task pre_body();
    `uvm_info(get_type_name(), "Pre Body", UVM_MEDIUM) // Print info message
  endtask : pre_body

  task post_body();
    `uvm_info(get_type_name(), "Post Body", UVM_MEDIUM) // Print info message
  endtask : post_body
*/
  endclass

🔍 Explanations
#

  • body(): The main working part of the sequence. It generates 20 random adder_packet items and sends them to the sequencer-driver structure.

🔹 uvm_do is a convenient macro in UVM that creates a sequence item or sequence, randomizes it, and sends it to a sequencer.

✅ Its responsibilities:

  • Calls create() to instantiate the object.
  • Calls randomize() to apply randomization.
  • Calls start_item() and finish_item() to send the item to the sequencer.

This allows you to create, randomize, and send the item to the driver all in one line! 🚀


💡 Summary
#

🔹 uvm_sequence is the backbone of UVM’s stimulus generation mechanism.
🔹 It makes test scenarios modular and reusable.
🔹 The adder example demonstrates how to model a simple addition test environment using adder_packet sequence items.
🔹 The pre_body() and post_body() methods give users additional customization and logging opportunities.


UVM Series - This article is part of a series.
Part 12: This Article

Related

UVM Agent Usage and Adder Example
· loading · loading
Education UVM Verification UVM Verification SystemVerilog Uvm_agent Testbench Structure
Education UVM Verification
UVM Monitor Usage and Adder Example
· loading · loading
Education UVM Verification UVM Verification SystemVerilog Uvm_monitor Coverage
Education UVM Verification
UVM Scoreboard Usage and Adder Example
· loading · loading
Education UVM Verification UVM Verification SystemVerilog Uvm_scoreboard Test Results
Education UVM Verification
UVM Sequence Item and Data Modeling
· loading · loading
Education UVM Verification UVM Verification SystemVerilog Data Modeling Uvm_sequence_item
Education UVM Verification
UVM Test Usage and base_test Example
· loading · loading
Education UVM Verification UVM Verification SystemVerilog Uvm_test Test Scenario
Education UVM Verification
UVM Base Classes
· loading · loading
Education UVM Verification UVM Verification SystemVerilog Class Hierarchy
Education UVM Verification