SystemVerilog Blocking vs Non-Blocking Assignments Explained

⛓️ Blocking vs Non-Blocking Assignments in SystemVerilog

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SystemVerilog provides two types of procedural assignments inside always or initial blocks:

➡️ Blocking Assignment (=)

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• Executes immediately and in sequence
• Each line blocks the next until it’s done
• Typically used in combinational logic

✅ Example:

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always @(*) begin
  a = b;
  c = a;  // uses updated 'a'
end

Think: Like normal programming assignments (step-by-step).

⏩ Non-Blocking Assignment (<=)

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• Schedules the update — doesn’t happen immediately
• Allows all right-hand sides to be evaluated before updating left-hand sides
• Used in sequential (clocked) logic

✅ Example:

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always @(posedge clk) begin
  a <= b;
  c <= a;  // 'a' is not updated yet, uses old value
end

Think: Like flip-flop behavior — values update at the end of the clock cycle.

🧠 Best Practice

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❗ Never mix = and <= in the same always block — it can lead to confusing and incorrect simulation behavior.