SystemVerilog Conditional Statements – if-else, case, unique, and priority

🧠 SystemVerilog Conditional Statements

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Conditional constructs are essential in hardware and behavioral modeling. SystemVerilog provides powerful decision-making structures with enhanced features beyond traditional Verilog:

• if-else for general condition checking
• case, casex, and casez for multi-way selection
• unique and priority modifiers to guide synthesis and detect errors
• ternary operator for concise conditional assignments

🔹 if / else Statement

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The fundamental conditional construct that selects between execution paths.

if (enable) begin
  data_out = data_in;
  valid = 1'b1;
end
else begin
  data_out = 0;
  valid = 1'b0;
end

✅ Good For:

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• Simple 2-way or multi-level conditionals
• Clear, readable combinational logic
• Sequential logic in always_ff blocks

⚠️ Watch Out:

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• Incomplete if-else in combinational logic infers latches
• Nested if-else can create priority routing in synthesis

🔹 case Statement

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A powerful multi-branch conditional structure with several variants:

1. Standard case

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case (opcode)
  4'b0000: result = a + b;
  4'b0001: result = a - b;
  4'b0010: result = a << 1;
  default: result = 0;
endcase

2. casez (treats ‘z’ as don’t-care)

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casez (instruction)
  8'b1??????? : process_immediate();
  8'b01?????? : process_register();
  default     : illegal_opcode();
endcase

3. casex (treats ‘x’ and ‘z’ as don’t-care)

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casex (ctrl_bits)
  4'b1xxx : high_priority();
  4'b01xx : medium_priority();
  default : low_priority();
endcase

🛠️ Pro Tips:

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• Always include a default branch in combinational logic
• casez is safer than casex for synthesis
• Use bit masks instead of ? for better readability

🔹 Ternary Conditional Operator

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Compact conditional assignment:

assign out = (sel) ? in1 : in0;

Best for:

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• Simple mux implementations
• Parameter assignments
• Constant expressions

🔹 unique / priority Modifiers

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SystemVerilog introduces powerful qualifiers to clarify design intent:

🔸 unique case / if

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Guarantees that only one condition will match. Generates errors if:

• No branches match (runtime warning)
• Multiple branches match (runtime error)

unique case (state)
  IDLE  : next_state = READ;
  READ  : next_state = PROCESS;
  WRITE : next_state = IDLE;
endcase

🔸 priority case / if

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Ensures at least one branch will execute, evaluating in order:

priority if (irq[3]) handle_irq3();
else if (irq[2]) handle_irq2();
else if (irq[1]) handle_irq1();

🚀 Advanced Usage:

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unique if (mode inside {SINGLE, BURST}) begin
  // Only one mode can be active
end

🧪 Simulation and Synthesis Behavior

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⚠️ Modern tools use these hints for optimization and safety checking

⚙️ Synthesis Considerations

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• Regular if may create priority routing if deeply nested
• case typically generates balanced multiplexers
• unique case enables one-hot optimization
• priority if creates cascading logic (like if-else chains)
• Ternary operators often synthesize to compact muxes

🔍 Key Insight:

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// These may synthesize differently:
if (sel) out = a; else out = b;  // Potential priority routing
assign out = sel ? a : b;        // Usually cleaner mux

📌 Comprehensive Comparison Table

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✅ Professional Best Practices

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1. For FSMs: Always use unique case for state decoding
2. For interrupt handling: Use priority if for clear precedence
3. For combinational logic:
   • Either cover all cases explicitly
   • Or use default assignments at the top
4. For readability:
   • Keep conditions simple
   • Use parentheses for complex expressions
   • Add comments for non-obvious conditions

🏆 Pro Tip:

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// Good practice - defensive coding
always_comb begin
  // Default assignment
  result = 0;
  
  // Override in specific cases
  unique case (op)
    ADD: result = a + b;
    SUB: result = a - b;
  endcase
end

🚀 Performance Considerations

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1. Critical Paths:

   • priority if creates longer paths
   • unique case generally has balanced timing

2. Area Optimization:

   • Ternary operators often yield smallest muxes
   • case statements are typically well-optimized

3. Power Implications:

   • unique constructs enable clock gating opportunities
   • Nested if may prevent power optimization

🔖 Key Insight

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unique if (mode inside {IDLE, RUN, WAIT}) 
  // Only one mode can be active