SystemVerilog Structures and User-Defined Types

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🏗️ What is a Struct?

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A struct in SystemVerilog is a composite data type that groups different data types into a single logical unit. Similar to structures in C/C++, it allows you to organize related variables under one name.

🔹 Key Features of Structs:

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• Heterogeneous data grouping (different types in one structure)
• Modular data organization
• Improves code readability
• Ideal for data packing and protocol modeling

🔹 Basic Struct Syntax:

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struct {
  data_type1 member1;
  data_type2 member2;
  // ...
} struct_name;

🔹 Example Struct Definition:

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struct {
  string    name;
  int       age;
  logic[3:0] id;
  bit       is_active;
} employee;

🔹 Packed vs. Unpacked Struct:

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• Packed Struct: Bit-accurate, contiguous memory allocation

  struct packed {
    logic [7:0] r;
    logic [7:0] g;
    logic [7:0] b;
  } pixel_t;
  

• Unpacked Struct: Default, more flexible (members may not be contiguous)

🔹 Accessing Struct Members:

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employee.name = "Ahmet";
employee.age = 32;
if (employee.is_active) ...

🔹 Using typedef with Structs (Best Practice):

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typedef struct {
  logic [31:0] addr;
  logic [63:0] data;
  logic        valid;
} transaction_t;

transaction_t trx;

Structs are widely used in SystemVerilog for data packets, protocol messages, and complex data structures in RTL and verification.

🔄 Understanding Unions in SystemVerilog

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Unions allow a single storage location to be accessed as different data types, providing memory-efficient ways to represent data that can be interpreted in multiple ways.

🔹 Key Features of Unions:

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• Shared memory space for all members
• Only one member active at a time
• Memory-efficient for alternative data representations
• Useful for protocol processing and hardware register modeling

🔹 Basic Union Syntax:

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union {
  data_type1 member1;
  data_type2 member2;
  // ...
} union_name;

🔹 Packed vs Unpacked Unions:

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• Packed Union: All members share exact same bit width

  union packed {
    logic [31:0] int_val;
    logic [7:0]  byte_arr[4];
  } data_u;
  

• Unpacked Union: Members can have different sizes (less common)

🔹 Practical Union Example:

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typedef union {
  int     as_int;
  shortreal as_float;
  logic [31:0] as_bits;
} number_u;

number_u num;
num.as_float = 3.14;  // Store as float
$display("Integer view: %0d", num.as_int);  // Reinterpret as int

🔹 Union with Struct:

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typedef struct {
  logic [7:0] addr;
  union {
    logic [31:0] data;
    logic [7:0]  bytes[4];
  } payload;
} packet_t;

🔹 Common Use Cases:

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1. Protocol Processing (different interpretations of same bits)
2. Hardware Register Access (multiple views of same register)
3. Type Conversion (bit reinterpretation without casting)
4. Memory Optimization (when only one variant is needed at a time)

🔹 Important Notes:

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• Only the last written member should be read
• No type checking - programmer must track active member
• Packed unions are synthesizable (unpacked unions typically aren’t)
• Use with caution in verification due to potential type safety issues

🔹 Union vs Struct Comparison:

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🏷️ SystemVerilog User-Defined Types and Type Aliases

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SystemVerilog allows users to define custom data types using the typedef keyword. This feature enhances code readability, reusability, and type abstraction, especially in large RTL or verification projects.

🔤 What is typedef?

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The typedef keyword creates an alias (alternative name) for an existing data type or a complex type definition.

Basic Syntax:

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typedef original_type alias_name;

✅ Why Use typedef?

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• Improves readability for complex types
• Simplifies parameter passing in tasks/functions
• Enables strong typing and abstraction
• Reduces code duplication

📌 Examples of typedef Usage

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1. Simple Alias

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typedef logic [7:0] byte_t;
byte_t a, b;  // Equivalent to: logic [7:0] a, b;

2. Typedef for Structs

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typedef struct {
  string name;
  int    age;
  bit    is_valid;
} person_t;

person_t user1;
user1.name = "Kerim";

3. Typedef for Enums

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typedef enum logic [1:0] {
  IDLE,
  RUN,
  DONE
} state_t;

state_t fsm_state;

4. Typedef for Arrays

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typedef logic [15:0] word_t;
typedef word_t mem_array_t [0:255];  // 256-word memory

mem_array_t my_ram;

5. Typedef for Unions

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typedef union packed {
  int    as_int;
  byte_t as_bytes[4];
} data_u;

data_u data;

🔁 Using typedef with Parameterized Types

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You can define flexible and reusable types inside parameterized modules or interfaces:

module fifo #(parameter WIDTH = 8) ();
  typedef logic [WIDTH-1:0] data_t;
  data_t buffer;
endmodule

🧩 Struct Assignment Styles in SystemVerilog

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SystemVerilog provides flexible methods to assign values to struct elements — both member-wise and aggregate-based.

1. Individual Member Assignment

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You can assign each member of a struct one by one:

employee.name      = "Ali";
employee.age       = 30;
employee.id        = 4'b1100;
employee.is_active = 1;

2. Aggregate Assignment (Literal Initialization)

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You can assign the entire struct using a literal list ('{...}), in declaration or at runtime:

employee = '{ "Ayşe", 28, 4'b0011, 1 };

✅ Order must match the declaration order of struct members.

You can also use named assignments for clarity:

employee = '{
  name: "Zeynep",
  age: 25,
  id: 4'b1001,
  is_active: 0
};

🧠 Named assignments make your code self-documenting and less error-prone.

3. Default Value Initialization

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SystemVerilog allows partial or full default initialization using the default: keyword:

employee = '{logic: 0, default: 0};   // All fields reset to 0 or "", All logic kind variable reset to 0

This is especially useful in testbenches and struct arrays.

🚨 Notes and Best Practices

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• Use _t suffix to indicate type aliases (e.g., byte_t, state_t)
• typedef cannot define a new class—only primitive types, structs, enums, unions, or arrays
• Highly useful in testbenches, UVM components, and interfaces

📚 Summary Table

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