SystemVerilog Arrays

📦 SystemVerilog Arrays

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SystemVerilog extends the concept of arrays far beyond Verilog’s basic vectors. It introduces multiple powerful array types that allow for better data organization, random access, and dynamic behavior during simulation and testbench development.

🧱 1. Packed Arrays (Bit Vectors)

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Packed arrays represent contiguous bits stored together — they are used like traditional Verilog vectors.

logic [7:0] byte_data;  // 8-bit packed vector

• Always declared left-to-right ([MSB:LSB])
• Treated as a single value in arithmetic and bitwise operations
• Can be multi-dimensional:

logic [3:0][7:0] memory_word;  // 4 elements, each 8 bits

📚 2. Unpacked Arrays

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Unpacked arrays are true arrays of elements, each stored separately.

logic [7:0] memory_array [0:15];  // 16 elements, each 8 bits
logic arr [8]; // single dimensional equals  [7:0]
logic arr [8][2]; // [7:0] [1:0]

• Declared to the right of the variable name
• Useful for RAMs, register files, lookup tables, etc.
• Multidimensional versions are supported:

logic [7:0] matrix [0:3][0:3];  // 4x4 byte matrix

🔁 3. Dynamic Arrays

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Dynamic arrays are arrays whose size can change during simulation.

int dyn_array[];
dyn_array = new[10];    // Allocate 10 elements
dyn_array[0] = 5;

• Only allowed in simulation/testbenches
• Useful when the size is not known at compile-time
• Support methods like .size(), .delete()
• Use new(number) to allocate size

$display("Size = %0d", dyn_array.size());
dyn_array.delete();  // Deallocate

🧠 4. Associative Arrays

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Associative arrays use arbitrary data types as an index (e.g., string, int).

int aa[string];       // Associative array indexed by string
aa["apple"] = 3;
aa["banana"] = 5;

• Index types can be: int, string, enum, etc.

• Useful for sparse data or lookups

• Provide advanced methods like:

  • .exists(key)
  • .first(index)
  • .next(index)
  • .num()

if (aa.exists("apple")) $display("Found apple");

🪜 5. Queues

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Queues are like dynamic arrays with FIFO (First-In-First-Out) behavior.

int q[$];       // Queue of ints
q.push_back(1);
q.push_back(2);
q.push_front(0);

• Use $ to declare an unbounded queue

• Common queue methods:

  • .push_front(), .push_back()
  • .pop_front(), .pop_back()
  • .insert(index, value), .delete(index)
  • .size(), .empty()

int x = q.pop_front();

📏 Summary Table

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🛠️ Tip: Combining Packed and Unpacked Arrays

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You can combine both packed and unpacked arrays to describe memory blocks:

logic [31:0] mem_array [0:1023];  // 1024 words, each 32 bits

Here:

• [31:0] is packed (bit vector)
• [0:1023] is unpacked (array of entries)

🧩 Array Assignment Styles in SystemVerilog

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SystemVerilog provides multiple ways to assign values to arrays, depending on whether they are packed, unpacked, dynamic, associative, or queues.

1. Index-Based Assignment

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Classic style: assign a specific index manually.

arr[0] = 8'hAA;

2. Array Literal (Aggregate) Assignment

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Assign an entire array at once using '{'} literal syntax:

logic [7:0] arr [0:3];
initial arr = '{8'h11, 8'h22, 8'h33, 8'h44};

• Also works with default: for partial or uniform initialization:

arr = '{default: 8'h00};  // Zero all elements

✅ Best Practices

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• Use packed arrays in RTL for efficient synthesis
• Use dynamic, associative, and queue arrays in testbenches
• Prefer queues for scoreboards and transaction FIFOs
• Use methods (.size(), .exists()) to write safe and scalable test code

This modular array system is one of the key strengths of SystemVerilog, enabling both hardware modeling and high-level software-like testbench structures.