SystemVerilog always_ff vs always_comb vs always_latch – Safe RTL Coding Explained

🔁 always_ff vs always @(posedge clk)

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✅ Why always_ff is Superior

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SystemVerilog’s always_ff is a strictly enforced sequential logic block that eliminates common pitfalls of Verilog’s always @(posedge clk):

• Compiler-enforced rules:
  • Only non-blocking assignments (<=) allowed.
  • Prohibits mixing combinational/sequential logic.
  • Accepts only variables (no wire assignments).
• Guaranteed synthesis-simulation alignment.

always_ff @(posedge clk or posedge rst) begin  
  if (rst)  
    q <= 0;  
  else  
    q <= d;  
end  

⚠️ Critical: Using blocking assignments (=) in always_ff causes a compiler error.

⚙️ always_comb vs always @(*)

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✅ Key Advantages of always_comb

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always_comb begin  
  y = my_func(sel);  // Auto-tracks ALL inputs (even in `my_func`).  
end  

🚫 Restriction: No delays (e.g., #5) allowed in always_comb.

🧠 Hidden Pitfall: Function Sensitivity in always @(*)

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❌ Buggy Verilog Example

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function logic [3:0] my_func(input logic flag);  
  if (flag) return a + b;  // `a` and `b` NOT in sensitivity list!  
  else      return a - b;  
endfunction  

always @(*) begin  
  y = my_func(sel);  // ❌ Fails if `a`/`b` change (no re-evaluation).  
end  

✅ Fixed with always_comb

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always_comb begin  
  y = my_func(sel);  // ✅ Auto-detects `a`, `b`, and `sel`.  
end  

🕳️ always_latch – Intentional Latch Design

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🎯 When to Use

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Only for explicit level-sensitive latches:

always_latch begin  
  if (en) q = d;  // Latches value when `en` is low.  
end  

🔍 Tool Warnings:

• Triggers if edge-sensitive logic (e.g., posedge) is used.
• Infers latches on incomplete branches (no else).

📚 Quick Reference Table

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✅ Best Practices

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1. Always prefer always_ff/always_comb over legacy Verilog.
2. Never mix = and <= in the same block.
3. Default assignments: Initialize outputs in always_comb to avoid latches.
4. Functions/Tasks: Use always_comb to auto-track all dependencies.

🔥 SystemVerilog’s always_* blocks are industry standards for unambiguous, synthesis-safe RTL design.