🧠 SystemVerilog Unsized Literals#
📘 Recommended Read: 👉 check out the Verilog Data Types Guide.
In SystemVerilog, the following statement:
data = '0;
means:
“Assign zero to all bits of the
datasignal.”
This syntax uses an unsized literal (0) preceded by a single quote ('). SystemVerilog automatically adjusts the bit-width of the right-hand side value to match the size of the left-hand side variable.
✅ Example#
logic [31:0] data;
data = '0; // Equivalent to: data = 32'b0;
You don’t need to manually specify the bit-width — the '0 literal is automatically extended with zeros to match the full width of data.
🔍 Why Is It Safe?#
Literals like 'hFF come with fixed bit-widths, whereas '0 and '1 are considered single-bit values that get replicated across all bits of the target variable.
For example:
logic [7:0] a = '1; // a = 8'b11111111
logic [15:0] b = '0; // b = 16'b0000000000000000
🔖 Note#
Using literals like
'0 and '1 in this way is a clear, concise, and synthesis-friendly coding style.
It’s widely recommended for resetting or initializing signals in SystemVerilog.module unsized_literals_tb;
// Logic signals with different widths
logic [7:0] a;
logic [15:0] b;
logic [31:0] c;
logic signed [15:0] d;
initial begin
// Assign using unsized literals
a = '1; // All bits set to 1: 8'b11111111
b = '0; // All bits set to 0: 16'b0000_0000_0000_0000
c = '1; // All bits set to 1: 32'b1...1
d = '0; // Works for signed signals too
// Print results
$display("a (8-bit) = %b", a);
$display("b (16-bit) = %b", b);
$display("c (32-bit) = %b", c);
$display("d (signed) = %b", d);
// Alternative: make all bits unknown (X)
a = 'x;
$display("a = 'x -> %b (all bits unknown)", a);
// Alternative: make all bits high impedance (Z)
b = 'z;
$display("b = 'z -> %b (all bits high impedance)", b);
end
endmodule
📤 Output:#
# a (8-bit) = 11111111
# b (16-bit) = 0000000000000000
# c (32-bit) = 11111111111111111111111111111111
# d (signed) = 0000000000000000
# a = 'x -> xxxxxxxx (all bits unknown)
# b = 'z -> zzzzzzzzzzzzzzzz (all bits high impedance)