SystemVerilog Enum Data Type

In SystemVerilog, an enum is a data type used to group named constant values. It improves code readability, reduces error risk, and simplifies debugging.

enum {RED, GREEN, BLUE} led_color;

🧠 Why Use `enum`?
#

With `parameter`	With `enum`
`parameter RED = 0;`	`enum {RED, GREEN, BLUE}`
Only numeric values visible	Named constants improve clarity
No type safety	Variable only accepts enum values
Hard to manage `default`	Easier to detect invalid cases

✅ Basic Usage
#

module led_ctrl;
  enum {RED, GREEN, BLUE} color;

  initial begin
    color = GREEN;
    if (color == RED)
      $display("Red selected!");
  end
endmodule

🔄 By default, values are assigned as RED = 0, GREEN = 1, BLUE = 2. You can assign your values : enum {RED = 5, GREEN =7 , BLUE} color; // blue default get 1 after value befor so 8.

🧰 Enum Methods (Built-in)
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SystemVerilog enums support several helpful built-in methods:

Method	Description
`first()`	Returns the first enum value
`last()`	Returns the last enum value
`next(value)`	Returns the next value after `value`
`prev(value)`	Returns the previous value before `value`
`num()`	Returns the number of enum elements
`name(value)`	Returns the string name of the enum constant

🧠 These methods are simulation-only and not synthesizable.

🧪 Example: Printing All Enum Constants
#

module enum_list_example;
  enum {IDLE, READ, WRITE, ERROR} state;

  initial begin
    repeat(state.num()) begin
      $display("State = %s", state.name());
    end
  end
endmodule

📤 Output:
#

State = IDLE
State = READ
State = WRITE
State = ERROR

This technique allows printing all enum constant names in a readable way to the terminal or log file.

⚠️ Things to Keep in Mind
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Methods like name() are only for simulation and not synthesizable.
For broader reuse, defining enum types with typedef is recommended — to be covered in the next article.

📌 Summary
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enum allows you to define constants that are safer and more readable.
A better alternative to raw parameter definitions.
Methods like name() enhance testbench logging and debugging.
Usable in RTL, but some features are only supported during simulation.

module enum_demo_tb;

  typedef enum logic [1:0] {
    RED,
    GREEN,
    BLUE
  } color_t;

  color_t led_color;
  color_t temp;

  initial begin
    // Basic usage
    led_color = GREEN;
    if (led_color == RED)
      $display("🔴 Red selected!");
    else if (led_color == GREEN)
      $display("🟢 Green selected!");
    else
      $display("🔵 Blue selected!");

    // Enum methods
    $display("\n🧪 Enum Built-in Methods:");
    temp = led_color.first();
    $display("First value  : %s", temp.name());
    temp = led_color.last();
    $display("Last value   : %s", temp.name());
    $display("Total enums  : %0d", led_color.num());

    temp = led_color.next(RED);
    $display("Next of RED  : %s", temp.name());

    temp = led_color.prev(BLUE);
    $display("Prev of BLUE : %s", temp.name());

    // Print all enum constants
    $display("\n📋 Listing all enum constants:");
    for (int i = 0; i < led_color.num(); i++) begin
      temp = color_t'(i);  // Explicit cast required
      $display("Color %0d = %s", i, temp.name());
    end
  end

endmodule

# ? Green selected!
# 
# ? Enum Built-in Methods:
# First value  : RED
# Last value   : BLUE
# Total enums  : 3
# Next of RED  : GREEN
# Prev of BLUE : BLUE
# 
# ? Listing all enum constants:
# Color 0 = RED
# Color 1 = GREEN
# Color 2 = BLUE