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SystemVerilog String Data Type

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Verification SystemVerilog String Testbench Simulation File I/O Non-Synthesizable
Verification
Axolot Logic
Author
Axolot Logic
Digital Design Engineer
Table of Contents
SystemVerilog Design Series - This article is part of a series.
Part 4: This Article

🧵 What Is string?
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In SystemVerilog, the string type represents a dynamically sized sequence of characters. Unlike static byte or bit [7:0] arrays, it automatically adjusts size and manages memory.

string message;
message = "Hello, SystemVerilog!";

🧠 Key Features
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FeatureDescription
Dynamic lengthMemory automatically adjusts to fit character count
Null-terminatedEach string ends with \0
Built-in operatorsSupports {}(concatination), ==, .len(), .toupper(), and more
Testbench-friendlyIdeal for logging, messages, and file I/O during simulation

📦 Basic Usage
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  string s1, s2, full;
  s1 = "Axolot";
  s2 = "Logic";
  full = {s1 , " " , s2};
  $display("✅ Full string: %s", full);  // Output: Axolot Logic

🔧 Common String Methods
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MethodDescriptionExample Use
.len()Returns string lengths.len() → 12
.toupper()Converts to uppercases.toupper()
.tolower()Converts to lowercases.tolower()
.compare()Compares two stringss1.compare(s2)
.substr(i, n)Extracts substrings.substr(2, 4)
.getc(i)Returns character at index is.getc(0)"H"
.putc(i)Replace character at index i"H"s.putc(0)

🧪 Using Strings in Testbenches
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In verification environments, string is perfect for naming, logging, error messages, or file operations:

string filename, test_id = "test.txt";
int file;

filename = $sformatf("results/run_%0d.log", test_id);
file = $fopen(filename, "w");
$fwrite(file, "Simulation started for ID: %0d\n", test_id);

🚫 Is string Synthesizable?
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No. SystemVerilog strings are for simulation only. They are not synthesizable and cannot be used in actual RTL implementations.

🧠 For RTL, use static arrays like byte[] or logic [7:0] instead.

module string_demo_tb;

  // Declare string variables
  string s1, s2, full;
  int length;
  string upper_str, lower_str, sub_str;
  byte first_char;

  // File I/O
  string filename;
  int file;
  int test_id = 42;

  initial begin
    // Basic assignment and concatenation
    s1 = "Axolot";
    s2 = "Logic";
    full = {s1 , " " , s2};
    $display("✅ Full string: %s", full);  // Output: Axolot Logic

    // String methods
    length     = full.len();
    upper_str  = full.toupper();
    lower_str  = full.tolower();
    sub_str    = full.substr(2, 4);
    first_char = full.getc(0);

    $display("🔍 Length        : %0d", length);
    $display("🔠 Uppercase     : %s", upper_str);
    $display("🔡 Lowercase     : %s", lower_str);
    $display("🔖 Substring     : %s", sub_str);
    $display("🆎 First char    : %s", first_char);

    // Comparing strings
    if (s1.compare("Axolot") == 0)
      $display("✔️ Strings match: %s", s1);
    else
      $display("❌ Strings differ!");

    // File handling with string
    filename = $sformatf("results/run_%0d.log", test_id);
    file = $fopen(filename, "w");
    if (file) begin
      $fwrite(file, "📂 Simulation log for test ID: %0d\n", test_id);
      $fclose(file);
      $display("📁 File written: %s", filename);
    end else begin
      $display("⚠️ Failed to open file: %s", filename);
    end
  end

endmodule

Simulation Log
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# ? Full string: Axolot Logic
# ? Length        : 12
# ? Uppercase     : AXOLOT LOGIC
# ? Lowercase     : axolot logic
# ? Substring     : olo
# ? First char    : A
# ?? Strings match: Axolot

📌 Summary
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  • string is ideal for simulation and verification environments.
  • It’s more readable and flexible than fixed-length character arrays.
  • It cannot be synthesized — use only in testbenches.

✨ Use string for logs, messages, and filenames — not for hardware!


🔖 Note
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The string type involves dynamic memory and runtime features. It should only be used in testbenches — not in synthesizable RTL. For hardware implementations, prefer logic [7:0] arrays or fixed-size buffers.

SystemVerilog Design Series - This article is part of a series.
Part 4: This Article

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