SystemVerilog Data Types

SystemVerilog supports all Verilog-2001 data types for backward compatibility, but modern designs are encouraged to use SystemVerilog’s enhanced type system. The table below outlines commonly encountered legacy types and their modern replacements:

📘 Recommended Read: 👉 check out the Verilog Data Types Guide.

📜 Legacy Data Types Table
#

Verilog Type	SystemVerilog Equivalent	Usage Status	Notes
`reg`	`logic`	⚠️ Deprecated	Use `logic` in RTL for better semantics and synthesis support
`wire`	`logic` or `wire`	⚠️ Mixed Use	Use `wire` only for multi-driver net connections
`integer`	`int`	⚠️ Limited Use	32-bit signed; prefer `int` in new code
`time`	`longint`	🧪 Simulation Only	Used for simulation time tracking; not synthesizable
`real`	`real`, `shortreal`	🧪 Simulation Only	64-bit (`real`) or 32-bit (`shortreal`) floating point; not synthesizable

graph LR
A[SystemVerilog Data Types] --> B[Base scalar]
A --> C[Component structures]
B --> D[bit, logic, int]
C --> E[struct, union]
C --> F[array, queue]

Types
#

Type	States	Size	Signed	Default Value	Category	Notes
`bit`	0, 1	1-bit (scalar or packed)	No	`0`	2-State	Use in simulations or when X/Z not needed
`logic`	0, 1, X, Z	1-bit (scalar or packed)	No	`X`	4-State	Preferred over `reg`; for synthesizable RTL
`reg`	0, 1, X, Z	1-bit (scalar or packed)	No	`X`	4-State	Legacy type; replaced by `logic`
`byte`	N/A	8-bit	Yes	`0`	Integer	Signed by default
`shortint`	N/A	16-bit	Yes	`0`	Integer
`int`	N/A	32-bit	Yes	`0`	Integer	Most common integer type
`longint`	N/A	64-bit	Yes	`0`	Integer
`integer`	N/A	≥32-bit (impl. defined)	Yes	`0`	Integer	Legacy from Verilog; prefer `int` or `longint`
`time`	N/A	64-bit	No	`0`	Timing	Used for simulation time tracking
`string`	N/A	Dynamic length	N/A	`""`	String	Supports `.len()`, `.putc()`, etc.

🔄 `reg` vs `logic`
#

// Verilog style
reg [7:0] counter;  // Only allowed inside procedural blocks

// SystemVerilog style
logic [7:0] counter; // Works in both 'assign' and 'always' blocks

✅ logic offers clearer semantics and better compatibility with synthesis and tooling. ❌ reg is legacy and not recommended for new RTL.

🔌 Guidelines for Using `wire`
#

module example(
  input  wire a,      // Still common for input ports
  output logic b      // Preferred modern output
);
  wire c;
  assign c = a & b;    // Use only for multi-driver connections

  logic d;             // Use for internal signals
endmodule

🎯 Rule: Use wire only when multiple drivers are required. Otherwise, prefer logic for clarity and safety.

📅 Type Migration Guide
#

Usage Context	Verilog Type	Recommended SystemVerilog Type
Combinational Logic	`reg`	`logic`
Counters/Variables	`integer`	`int` or `bit [31:0]`
Floating Point Ops	`real`	`shortreal` (32-bit)
Hardware Connections	`wire`	`logic` (single driver) or `wire`

🧪 Example: Mixed Legacy and Modern Types
#

module legacy_mix(
  input  wire clk,
  output logic [3:0] data
);
  integer i;             // Legacy signed 32-bit
  bit [31:0] j;          // Modern unsigned 32-bit

  always_ff @(posedge clk) begin
    i = -1;
    j = i;               // Signed to unsigned conversion
  end
endmodule

🧠 Both integer and int are 32-bit signed, but int is preferred in modern designs. bit holds only 0/1 and is ideal for 2-state modeling.

⚠️ Common Pitfalls
#

Signedness Issues with integer:

integer i = 32'hFFFF_FFFF; // Equals -1 (signed!)
bit [31:0] b = i;          // Still 32'hFFFF_FFFF, but unsigned

real Is Not Synthesizable:
- Only usable in testbenches
- Will be ignored or rejected by synthesis tools

🛠️ Initial Value & Multiple Driver Problem with `logic`
#

  logic [7:0] x;
  initial x = 8'hFF;
  always_ff @(posedge clk)
    x <= x + 1;

❗ In the example above, a logic variable is assigned an initial value (= 8'hFF) within an initial block and then reassigned in an always_ff block. ⚠️ A variable assigned within an always_ff block cannot be assigned in any other procedural block.

✅ To avoid this, choose following:

  logic [7:0] x;
  initial x = 8'hFF;
  always @(posedge clk)
    x <= x + 1;

✅ Best Practices for New Code
#

Use logic instead of reg for synthesizable RTL.
Use bit, int in testbenches for simpler simulation and better performance.
Use wire only when multiple drivers are necessary.
Replace integer with int, and real with shortreal where applicable.
Be cautious when assigning initial values to logic in FPGA code.

module datatype_testbench;

  // Data type declarations
  bit         b;
  logic       l;
  reg         r;
  wire        w;
  byte        bt;
  shortint    si;
  int         i;
  longint     li;
  integer     old_i;
  time        t;
  real        real_val;
  shortreal   sreal_val;
  string      str;

  assign w = b; // wire must be driven

  initial begin
    // Initial default values
    $display("----- [Initial Default Values] -----");
    $display("bit         = %b", b);
    $display("logic       = %b", l);
    $display("reg         = %b", r);
    $display("wire        = %b", w);
    $display("byte        = %0d", bt);
    $display("shortint    = %0d", si);
    $display("int         = %0d", i);
    $display("longint     = %0d", li);
    $display("integer     = %0d", old_i);
    $display("time        = %0t", t);
    $display("real        = %0f", real_val);
    $display("shortreal   = %0f", sreal_val);
    $display("string      = \"%s\" (length = %0d)", str, str.len());

    #5; // Wait for 5 time units

    // Assign signed values
    b         = -1'b1;
    l         = -1'b1;
    r         = -1'b1;
    bt        = -8'sd100;
    si        = -16'sd30000;
    i         = -32'sd12345678;
    li        = -64'sd1234567890123456;
    old_i     = -42;
    t         = -64'd500;
    real_val  = -3.141592;
    sreal_val = -2.71;
    str       = "SystemVerilog";

    $display("\n----- [Assigned Signed Values] / If signed it should negative -----");
    $display("bit         = %b", b);
    $display("logic       = %b", l);
    $display("reg         = %b", r);
    $display("wire        = %b", w);
    $display("byte        = %0d", bt);
    $display("shortint    = %0d", si);
    $display("int         = %0d", i);
    $display("longint     = %0d", li);
    $display("integer     = %0d", old_i);
    $display("time        = %0t", t);
    $display("real        = %0f", real_val);
    $display("shortreal   = %0f", sreal_val);
    $display("string      = \"%s\" (length = %0d)", str, str.len());

    // Bit widths using $bits()
    $display("\n----- [Bit Widths Using $bits()] -----");
    $display("$bits(bit)         = %0d", $bits(b));
    $display("$bits(logic)       = %0d", $bits(l));
    $display("$bits(reg)         = %0d", $bits(r));
    $display("$bits(byte)        = %0d", $bits(bt));
    $display("$bits(shortint)    = %0d", $bits(si));
    $display("$bits(int)         = %0d", $bits(i));
    $display("$bits(longint)     = %0d", $bits(li));
    $display("$bits(integer)     = %0d", $bits(old_i));
    $display("$bits(time)        = %0d", $bits(t));
    $display("real               = %0d", $bits(real_val));
    $display("shortreal          = %0d", $bits(sreal_val));
    $display("string             = \"%0d\" (uzunluk = %0d)", $bits(str), str.len());
    // Note: $bits() is not applicable to 'real', 'shortreal'
  end

endmodule

📤 Output:
#

# ----- [Initial Default Values] -----
# bit         = 0
# logic       = x
# reg         = x
# wire        = x
# byte        = 0
# shortint    = 0
# int         = 0
# longint     = 0
# integer     = x
# time        = 0
# real        = 0.000000
# shortreal   = 0.000000
# string      = "" (length = 0)
# 
# ----- [Assigned Signed Values] / If signed it should negative -----
# bit         = 1
# logic       = 1
# reg         = 1
# wire        = 0
# byte        = -100
# shortint    = -30000
# int         = -12345678
# longint     = -1234567890123456
# integer     = -42
# time        = -500
# real        = -3.141592
# shortreal   = -2.710000
# string      = "SystemVerilog" (length = 13)
# 
# ----- [Bit Widths Using $bits()] -----
# $bits(bit)         = 1
# $bits(logic)       = 1
# $bits(reg)         = 1
# $bits(byte)        = 8
# $bits(shortint)    = 16
# $bits(int)         = 32
# $bits(longint)     = 64
# $bits(integer)     = 32
# $bits(time)        = 64
# real               = 0
# shortreal          = 0
# string             = "104" (length = 13)