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SystemVerilog Assertions: Delay, Repetition, and Status

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Kerim Turak
Education SystemVerilog Verification SystemVerilog Assertion Verification Repetition Delay Overlap Go-to Repetition Assertion Status
Education SystemVerilog Verification
Author
Kerim Turak
Digital IC Design & Verification Engineer
Table of Contents
SystemVerilog Design Series - This article is part of a series.
Part 37: This Article

πŸ“ˆ Assertion Status
#

During the execution of an assertion, we can track various statuses:

  • Succeeded (pass): The assertion worked as expected.
  • Failed: The assertion condition was not met.
  • Inactive: The assertion is disabled or not triggered.
  • Active: The assertion condition is being checked; the assertion is triggered and running.
  • Enabled: The assertion is in an enabled state and ready to trigger when its condition occurs.

⏳ Cycle Delay Repetition
#

In a sequence or assertion, cycle delay expressions can be used to define delays across successive clock cycles.

Example:

sequence s_delay;
  a ##2 b;
endsequence

In this example, b is checked 2 cycles after a occurs.


πŸ”„ Cycle Delay Repetition Ranges
#

Using a range in delays allows us to define more flexible checks:

sequence s_range;
  a ##[2:4] b;
endsequence

Here:

  • b is checked 2 to 4 cycles after a occurs.

πŸ” Consecutive Repetition
#

Consecutive repetition checks whether an event occurs continuously over consecutive cycles.

Example:

sequence s_consec;
  (a && b)[*3];
endsequence

Here:

  • The expression a && b must be true for 3 consecutive cycles.

πŸ”‚ Consecutive Repetition with Ranges
#

You can also use ranges in consecutive repetitions:

sequence s_consec_range;
  (a && b)[*3:5];
endsequence

In this example:

  • The expression a && b must be true for 3 to 5 consecutive cycles.

🚦 Consecutive Repetition: Special Ranges
#

For special repetitions:

  • [*] βž” 0 or more consecutive cycles.
  • [+] βž” 1 or more consecutive cycles.

Example:

sequence s_star;
  a[*];
endsequence

sequence s_plus;
  b[+];
endsequence

⏸️ Nonconsecutive Repetition
#

Nonconsecutive repetition (or non-monitored repetition) checks whether an event occurs the desired number of times without requiring consecutive cycles. This typically uses the throughout or within keywords (advanced usage). Simple example:

sequence s_nonconsec;
  a ##[1:$] b;
endsequence

Here:

  • After a occurs, b is checked at least 1 cycle later, up to infinity.

πŸŒ€ Go-To Repetition
#

Go-To repetition allows an event to overlap in consecutive cycles, starting new instances. This is often used in FSM state assertions.

Example:

sequence s_goto;
  a ##1 b [->3];
endsequence

In this example:

  • The b signal is checked 3 times with parallel instances overlapping.

πŸ”€ Go-To and Nonconsecutive Ranges
#

Go-To repetition also supports ranges:

sequence s_goto_range;
  a ##1 b [->2:5];
endsequence

Here:

  • The b signal starts between 2 and 5 overlapping instances (non-deterministic).

πŸ“Š Repetition Table
#

SyntaxMeaning
[*]0 or more consecutive cycles
[+]1 or more consecutive cycles
[N]Exactly N consecutive cycles
[N:M]N to M consecutive cycles
[->N]Go-To, N overlapping instances
[->N:M]Go-To, N to M overlapping instances

SystemVerilog Design Series - This article is part of a series.
Part 37: This Article

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