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Immediate Assertion

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Kerim Turak
Education SystemVerilog Verification SystemVerilog Assertion Verification Immediate Assertion Deferred Immediate Assertion Design Verification
Education SystemVerilog Verification
Author
Kerim Turak
Digital IC Design & Verification Engineer
Table of Contents
SystemVerilog Design Series - This article is part of a series.
Part 33: This Article

🚦 What is an Immediate Assertion?
#

Immediate assertions are assertions that are used inside procedural blocks (initial, always, always_ff, always_comb, etc.) and are evaluated immediately. They are used for combinational checks and to catch errors right away.

Example:

always_ff @(posedge clk) begin
  assert (data_valid) else $error("Data not valid!");
end

This construct checks data_valid on every clock edge and prints an error message if it fails.


⏳ What is a Deferred Immediate Assertion?
#

Deferred immediate assertions are also used inside procedural blocks but defer their check to the next delta cycle. This means the check is not done immediately but after the block finishes. This is useful for ensuring data consistency, especially with non-blocking assignments.

Example:

always_ff @(posedge clk) begin
  x <= y; // non-blocking assignment
  assert final(x == y); // deferred immediate assertion
  // assert #0 (x == y); // deferred immediate assertion
end

Here, the final keyword marks it as a deferred immediate assertion, and the assertion is evaluated after the block completes (at the delta cycle).

Immediate vs. Deferred Immediate
#

FeatureImmediateDeferred Immediate
Execution timeInside the blockAt the end of the block
Code compatibilityBlocking assignmentNon-blocking assignment
Use caseQuick checkData consistency check

SystemVerilog Design Series - This article is part of a series.
Part 33: This Article

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