Named Events in SystemVerilog

📌 Named Events in SystemVerilog

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Named events are fundamental constructs in SystemVerilog for synchronizing concurrent processes. They provide a simple yet powerful way to signal when an action occurs, enabling processes to wait for or trigger specific conditions. Named events are widely used in testbenches and hardware modeling.

🗂️ What is a Named Event?

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A named event is a special SystemVerilog data type used for signaling between processes:

• Events can be triggered using the -> operator.
• Processes can wait for an event using the @ operator.

Named events are lightweight compared to semaphores or mailboxes, making them ideal for simple synchronization tasks like start/stop signals or phase notifications.

🛠️ Declaring and Using a Named Event

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📌 Declaration

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event my_event;

🔔 Triggering an Event

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Use the -> operator to trigger the event, unblocking any process waiting on it.

-> my_event;

This is a one-shot trigger — the event state itself is not persistent beyond the current time step.

⏳ Waiting for an Event

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Processes can wait for an event using the @ operator:

@(my_event);

This blocks the process until the event is triggered.

🛡️ Persistent Trigger Check

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To avoid race conditions when both the waiting and the triggering process occur in the same simulation time step, use the .triggered built-in method:

wait (my_event.triggered);

This ensures the process will unblock even if the event was triggered earlier in the same time step.

🔀 Combining Events

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You can assign one event to another to merge their synchronization queues:

event a, b;
a = b; // triggers on 'a' also trigger on 'b'

This allows processes waiting on either event to synchronize together.

🔍 Summary of Key Operations

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🛡️ Common Uses

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• Simulation Phase Control: Start/stop clock signals or reset signals.
• Testbench Synchronization: Coordinate phases in UVM or other verification frameworks.
• Process Coordination: Synchronize stimulus generation with scoreboards or monitors.

💡 Best Practices

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✅ Use .triggered to avoid race conditions in simulation cycles.
✅ Be cautious when merging events (a = b;) — processes waiting before the assignment may never unblock.
✅ Document event usage in the testbench to maintain clarity.

📖 Conclusion

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Named events are a lightweight yet essential tool for process synchronization in SystemVerilog. When used effectively, they enhance testbench clarity and coordination, enabling efficient simulation of complex designs.

module tb_named_event_demo;

  event start_event;  // Declare a named event
  logic clk = 0;

  // Clock generation
  always #5 clk = ~clk;

  // Stimulus process: triggers the event
  initial begin
    #15;
    $display("[Stimulus] Triggering event at time %0t", $time);
    -> start_event;  // Trigger the event
  end

  // Process that waits for the event
  initial begin
    $display("[Monitor] Waiting for event...");
    @(start_event);  // Wait for the event to be triggered
    $display("[Monitor] Event detected at time %0t", $time);
  end

  // Additional demonstration of .triggered usage
  initial begin
    #10;
    wait (start_event.triggered);
    $display("[Monitor] Event detected (using .triggered) at time %0t", $time);
  end

  // Simulation end
  initial begin
    #50;
    $finish;
  end

endmodule