SystemVerilog Randomization – $urandom, randcase, and randsequence

SystemVerilog offers several randomization utilities that can be used directly in testbenches without needing classes or OOP concepts.
These are ideal for simple stimulus generation, control signals, edge-case exploration, and data fuzzing.

🧮 `$urandom()` and `$urandom_range()`
#

The most common functions for generating random values are:

$urandom();              // 32-bit unsigned random value
$urandom_range(min, max);  // Random number between min and max

✅ Example
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initial begin
  int rand_num;
  rand_num = $urandom();
  $display("Random: %0d", rand_num);

  int bounded;
  bounded = $urandom_range(10, 20);
  $display("Bounded Random: %0d", bounded);
end

⚠️ $urandom() is unsigned — use casting if signed behavior is needed.

🎛️ Randomizing Bits and Signals
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You can assign random values directly to variables and wires:

logic [3:0] opcode;
initial opcode = $urandom_range(0, 15);  // 4-bit random value

You can also randomize arrays or vector slices:

logic [7:0] data [0:3];

initial begin
  foreach (data[i])
    data[i] = $urandom_range(0, 255);
end

🔁 `randcase`: Weighted Random Choice
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Use randcase to randomly select among branches based on weight:

initial begin
  randcase
    1: $display("Low Probability");
    3: $display("Medium");
    6: $display("High Probability");
  endcase
end

✅ Total weight doesn’t need to sum to 100 — just relative proportions matter.

📜 `randsequence`: Randomized Grammar
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randsequence allows randomized sequences based on production rules. Useful for generating random test vectors or signal transitions.

task automatic random_seq();
  randsequence
    expr : a '+' b;
    a    : 1 | 2 | 3;
    b    : 4 | 5;
  endsequence
endtask

⚠️ Supported in simulators for behavioral testing only — not synthesizable.

📊 Practical Use: Testbench Stimulus
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logic [7:0] stimulus;

initial begin
  repeat (10) begin
    stimulus = $urandom_range(0, 255);
    #10;
    $display("Stimulus = %0h", stimulus);
  end
end

🚫 `$random()` (Legacy)
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Verilog’s older $random() function returns signed 32-bit values but is not preferred due to:

Platform-dependent behavior
No seed control
Compatibility issues

✅ Prefer $urandom() and $urandom_range() for modern testbenches.

✅ Summary Table
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Feature	Syntax	Use Case
Basic random	`$urandom()`	General unsigned values
Ranged random	`$urandom_range(min, max)`	Bounded random value
Array/random fill	`foreach arr[i]` + `$urandom()`	Random array/data pattern generation
Weighted choice	`randcase`	Probabilistic behavior
Grammar gen	`randsequence`	Structured random sequences

SystemVerilog’s built-in randomization tools provide powerful yet simple methods for injecting variation into your testbenches — no class required! These are ideal for lightweight, scalable simulations and quick functional checks.

In the next tutorial, we’ll explore class-based randomization, constraints, and the rand/randomize() system.

module tb_randomization;

  logic [3:0] opcode;
  logic [7:0] data [0:3];
  logic [7:0] stimulus;

  initial begin
    // Basic random values
    int r1 = $urandom();
    int r2 = $urandom_range(10, 20);
    $display("Random     : %0d", r1);
    $display("Range 10-20: %0d", r2);

    // Randomizing signals
    opcode = $urandom_range(0, 15);
    $display("Opcode     : %0b", opcode);

    // Randomize array
    foreach (data[i]) begin
      data[i] = $urandom_range(0, 255);
      $display("data[%0d]   : %0h", i, data[i]);
    end

    // Weighted random case
    repeat (20) begin
      randcase
        3: $display("Selected: Low Prob");
        7: $display("Selected: Medium Prob");
        10: $display("Selected: High Prob");
      endcase
    end

    // Random stimulus loop
    repeat (5) begin
      stimulus = $urandom_range(0, 255);
      #5 $display("Stimulus   : %0h", stimulus);
    end
  end

endmodule