Kerim Turak

Property Reuse in SystemVerilog: Parameters, Arguments, and Assertion Binding

Using the cover directive in SystemVerilog and functional coverage

SystemVerilog Assertions: Delay, Repetition, and Status

SystemVerilog Sequence, Sequence Implication, and Usage

Connecting the UVM RAL Model to the Sequencer and Monitor

UVM RAL Predictor Usage: Keeping the Register Model Synchronized

SystemVerilog Assertions: Same Cycle and Next Cycle Implication

Using Concurrent Assertions in SystemVerilog

Creating and Integrating UVM RAL Register Model into the UVM Environment

UVM RAL Register API: Frontdoor and Backdoor Access

Immediate Assertion

UVM RAL: Memory, Address Map, and More

Using Boolean Expressions and Assertions in SystemVerilog

What is SystemVerilog Assertion (SVA) and Why Use It?

Using UVM RAL (Register Abstraction Layer) and Its Features

Using TLM Sockets in UVM with Example Code

Using the _decl Macro in UVM

Using TLM FIFO, Analysis Port, and _decl Macro in UVM

Using Blocking and Non-blocking Put/Get Ports in UVM

What is Transaction-Level Modeling (TLM) in UVM?

Virtual Sequences, Virtual Sequencers, Sequence Libraries, and Sequence Arbitration in UVM

UVM Sequence Starting Methods

Using uvm_subscriber in UVM Testbenches

Using UVM Configuration Classes

UVM Testbench Top Module and Adder Example

UVM Test Usage and base_test Example

UVM Environment Usage and adder_env Example

UVM Scoreboard Usage and Adder Example

UVM Agent Usage and Adder Example

UVM Monitor Usage and Adder Example

UVM Driver Usage and Adder Example

What is a UVM Sequencer and How to Use It?

UVM Sequence Usage and Adder Example

UVM Sequence Item and Data Modeling

Using the UVM Factory

UVM Phases: Testbench Lifecycle

Understanding uvm_component

UVM do_ Methods

Understanding uvm_object::print(), sprint(), sformat(), and convert2string()

UVM Utility Field Macros

UVM Object Class

UVM Base Classes

Getting Started with UVM: Setup and Supported Simulators

Introduction to UVM

SystemVerilog: Covergroups and Coverage

SystemVerilog: Class-Based Randomization and Constraints

Polymorphism and Virtuality in SystemVerilog

Advanced OOP in SystemVerilog: Aggregation, Inheritance, and More

Advanced OOP in SystemVerilog: Constructors, Handles, and Static Members

Object-Oriented Programming in SystemVerilog

Named Events in SystemVerilog

Mailboxes in SystemVerilog

Semaphores in SystemVerilog

Understanding Packages

Interprocess Synchronization and Communication in SystemVerilog

SystemVerilog Randomization – $urandom, randcase, and randsequence

SystemVerilog let Construct – Reusable Named Expressions for RTL and Assertions

SystemVerilog Package – Reusable Types, Constants, and Functions

SystemVerilog Clocking Block – Timing Control for Testbenches

SystemVerilog Interface – Modular Signal Grouping with modport and Clocking Blocks

SystemVerilog fork...join – Parallel Execution Explained

SystemVerilog Tasks and Functions

SystemVerilog Blocking vs Non-Blocking Assignments Explained

SystemVerilog Conditional Statements – if-else, case, unique, and priority

SystemVerilog Loops and Control Flow – for, while, foreach, repeat, break

SystemVerilog Structs, Unions, and Typedefs – User-Defined Data Types Explained

SystemVerilog Arrays

SystemVerilog always_ff vs always_comb vs always_latch – Safe RTL Coding Explained

SystemVerilog Modules – Structure, Instantiation, and RTL Best Practices

SystemVerilog Unsized Literals

SystemVerilog Enum Data Type

SystemVerilog String Data Type

RISC-V

UVM

SystemVerilog Logic Data Type

SystemVerilog Data Types

SystemVerilog

Verilog

SystemVerilog Intoduction

Verilog RTL Design & Testbench Best Practices

Verilog VCD: Waveform Dumping for Simulation Analysis

Verilog Namespaces: Understanding Scope and Modularity

Verilog Command-Line Input: $plusargs for Testbench Control

Verilog Compiler Directives & Macros: Conditional Compilation & Code Reuse

Verilog Synthesis: From RTL to Gate-Level Netlist

Verilog Hierarchical Reference: Accessing Internal Signals

Verilog System Functions & Tasks for Simulation

Verilog Delay Controls: #Delay, @Event, Wait

Verilog Simulation Basics & Testbench Design

Verilog Task vs. Function: Reusable Logic in HDL

Verilog Parameters: Making Modules Reusable & Configurable

Verilog Syntax Overview: Essentials for Digital Design

Verilog Blocking vs. Non-Blocking Assignments

Verilog Assignments: Procedural vs. Continuous Explained

Verilog generate Block: Parameterized Hardware Design

Verilog Control Flow: if, case, loops & RTL Guidelines

Verilog initial Block: Testbench & Simulation Essentials

Verilog Modules, Ports, Assignments & Best Practices

Verilog Data Types, Logic Values & Arrays Explained

Hardware Design Abstraction Levels in Verilog