Axolot Logic
Design, Verification, RISC-V
👋 Welcome to Axolot Logic#
Axolot Logic is your personal knowledge hub for HDL design, FPGA/ASIC development, and hardware verification. Whether you’re a beginner learning Verilog or an engineer exploring RTL techniques, this site offers concise tutorials and best practices.
📚 What You’ll Learn#
🧬 Verilog & SystemVerilog fundamentals
🔁 Simulation & waveform debugging
🧪 UVM & testbench architecture
⚙️ RTL coding styles & design abstraction
📐 Power-efficient & synthesizable hardware design
🚀 Start Here#
Check out these series to begin:
Warning! This course is not a standalone Verilog or SystemVerilog tutorial — it is specifically designed as a transition from Verilog to SystemVerilog.
graph LR
A(["⚡️Verilog HDL Series"]) --> B(["📈SystemVerilog Design"])
B --> C(["🚀Verification & UVM"])
click A href "/en/tutorials/verilog/" "Verilog Dersleri" _blank
click B href "/en/tutorials/systemverilog/" _blank
click C href "/en/tutorials/uvm/" _blank
style A fill:#facc15,stroke:#111,stroke-width:1px
style B fill:#60a5fa,stroke:#111,stroke-width:1px
style C fill:#34d399,stroke:#111,stroke-width:1px